Multi-bank dynamic random access memory devices having all bank precharge capability

ABSTRACT

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

This is a continuation of application Ser. No. 08/822,148 filed Mar. 17,1997, now U.S. Pat. No. 5,835,956.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory and, moreparticularly, to a synchronous dynamic random access memory which iscapable of accessing data in a memory cell array disposed therein insynchronism with a system clock from an external system such as acentral processing unit (CPU).

BACKGROUND INFORMATION

A computer system generally includes a CPU for executing instructions ongiven tasks and a main memory for storing data, programs or the likerequested by the CPU. To enhance the performance of the computer system,it is basically requested to increase the operating speed of the CPU andalso make an access time to the main memory as short as possible, sothat the CPU can operate at least with no wait states. Operation clockcycles of modern CPUs such as recent microprocessors are shortening moreand more as clock frequencies of 33, 66, 100 MHZ or the like. However,the operating speed of a high density DRAM, which is still the cheapestmemory on a price-per-bit base and using as a main memory device, hasnot been able to keep up with that of the CPU being speeded up. DRAMinherently has a minimum {overscore (RAS)} access time, i.e., theminimum period of time between activation of {overscore (RAS)}, uponwhich the signal {overscore (RAS)} changes from a high level to a lowlevel, and the output of data from a chip thereof with column addresseslatched by activation of {overscore (CAS)}. Such a {overscore (RAS)}access time is called a {overscore (RAS)} lately, and the time durationbe en the, activation of the signal {overscore (CAS)} and the output ofdata therefrom called a {overscore (CAS)} latency. Moreover, aprecharging time is required prior to re-access following the completionof a read operation or cycle. These factors decrease the total amount ofoperation speed of the DRAM, thereby causing the CPU to have waitstates.

To compensate for the gap between the operation speed of the CPU andthat of the main memory like the DRAM, the computer system includes anexpensive high-speed buffer memory such as a cache memory which isarranged between the CPU and the main memory. The cache memory storesinformation data from the main memory which is requested by the CPU.Whenever the CPU issues the request for the data, a cache memorycontroller intercepts it and checks the cache memory to see if the datais stored in the cache memory. If the requested data exists therein, itis called a cache hit, and high-speed data transfer is immediatelyperformed from the cache memory to the CPU. Whereas if there is nopresence therein, it is called a cache miss, and the cache memorycontroller reads out the data from the slower main memory. The read-outdata is stored in the cache memory and sent to the CPU. Thus, asubsequent request for this data may be immediately read out from thecache memory. That is, in case of the cache hit, the high-speed datatransfer may be accomplished from the cache memory. However, in case ofthe cache miss, the high-speed data transfer from the main memory to theCPU cannot be expected, thereby incurring wait states of the CPU. Thus,it is extremely important to design DRAMs serving as the main memory toaccomplish high-speed operations.

The data transfer between DRAMs and the CPU or the cache memory isaccomplished with sequential information or data blocks. To transfer thecontinuous data at a high speed, various kinds of operating modes suchas page, static column, nibble mode or the like have implemented in theDRAM. These operating modes are disclosed in U.S. Pat. Nos. 3,969,706and 4,750,839. The memory cell array of the DRAM with the nibble mode isdivided into four equal parts so that a plurality of memory cells can bemade access with the same address. Data is temporarily stored in a shiftregister to be sequentially read out or written into. However, since theDRAM with the nibble mode cannot continuously transfer more than 5-bitdata, the flexibility of the system design cannot be offered upon theapplication to high-speed data transfer systems. The page mode and thestatic column mode, after the selection of the same row address in a{overscore (RAS)} timing, can sequentially access column addresses insynchronism with {overscore (CAS)} toggling or cycles and with thetransition detections of column addresses, respectively. However, sincethe DRAM with the page or the static column mode needs extra time, suchas a setup and a hold times of the column address, for receiving thenext new column address after the selection of a column address, it isimpossible to access the continuous data at a memory bandwidth higherthan 100 Mbits/sec., i.e., to reduce a {overscore (CAS)} cycle timebelow 10 nsec. Also, since the arbitrary reduction of the {overscore(CAS)} cycle time in the page mode cannot guarantee a sufficient columnselection time to write data into selected memory cells during a writeoperation, error data may be written thereinto. However, since thesehigh-speed operation modes are not operations synchronous to the systemclock of the CPU, the data transfer system must use a newly designedDRAM controller whenever a CPU having higher speed is replaced. Thus, tokeep up with high-speed microprocessors such as CISC and RISC types, thedevelopment of a synchronous DRAM is required which is capable ofaccessing the data synchronous to the system clock of the microprocessorat a high speed. An introduction to synchronous DRAMs appears with nodisclosure of detailed circuits in the NIKKEI MICRODEVICES in April,1992, Pages 158-161.

To increase the convenience of use and also enlarge the range ofapplications, it is more desirable to allow an on-chip synchronous DRAMto not only operate at various frequencies of the system clock, but alsobe programmed to have various operation modes such as a latencydepending on each clock frequency, a burst length or size defining thenumber of output bits, a column addressing way or type, and so on.Examples for selecting an operation mode in DRAM are disclosed in U.S.Pat. No. 4,833,650 issued on May 23, 1989, as well as in U.S. Pat. No.4,987,325 issued on Jan. 22, 1991 and assigned to the same assignee.These prior art patents disclose technologies to select one operationmode, such as page, static column and nibble modes. Selection of theoperation mode in these prior art patents is performed by cutting offfuse elements by means of a laser beam from an external laser apparatusor an electric current from an external power supply, or by selectivelywiring bonding pads. However, in these prior technologies, once theoperation mode had been selected, the selected operation mode cannot bechanged into another operation mode. Thus, the prior art does not permitchanges between operation modes even if subsequently required.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a synchronous dynamicrandom access memory in which input/output of data is synchronous withan external system clock.

Another object of the present invention is to provide a synchronousdynamic random access memory with high performance.

Still another object of the present invention is to provide asynchronous dynamic random access memory which is capable of operatingat a high data transfer rate.

A further object of the present invention is to provide a synchronousdynamic random access memory which is able of operating at varioussystem clock frequencies.

Still a further object of the present invention is to provide asynchronous dynamic random access memory in which the number of input oroutput data may be programmed.

Another object of the present invention is to provide a counter circuitin which a counting operation can be performed in either binary orinterleave mode.

Still another object of the present invention is to provide asemiconductor memory which can prohibit unnecessary internal operationsof the memory chip regardless of the number of input or output data.

A further object of the present invention is to provide a semiconductormemory which can set various operation modes.

Still a further object of the present invention is to provide asemiconductor memory including a data transfer circuit for providingprecharge and data transfer operable at a high data transfer rate.

Another object of the present invention is to provide a semiconductormemory which includes at least two memory banks whose operation modescan be set in on-chip semiconductor memory.

According to an aspect of the present invention, a semiconductor memoryformed on a semiconductor chip having various operation modes, includesaddress input circuit for receiving external address designating atleast one of the operation modes to the chip, a circuit for generating amode set control signal in a mode set operation; and a circuit forstoring codes based on the external address in response to the mode setcontrol signal and producing an operation mode signal representing theoperation mode determined by the codes.

According to another aspect of the present invention, a semiconductormemory having a plurality of internal operation modes includes a circuitfor producing a power-on signal upon reaching of a power supplypotential at a predetermined value after the application of the powersupply potential, and a circuit for automatically storing a plurality ofcode signals in response to the power-on signal and producing internaloperation mode signals indicating selected ones of the internaloperation modes which are defined by the code signals.

According to another aspect of the present invention, a dynamic randomaccess memory includes a plurality of memory banks, each bank includinga plurality of memory cells and operable in either an active cycleindicating a read cycle or a write cycle, or a precharge cycle, a firstcircuit for receiving a row address strobe signal and producing a firstsignal, a second circuit for receiving a row address strobe signal andproducing a first signal, a second circuit for receiving a columnaddress strobe signal and producing a second signal, a third circuit forreceiving a write enable signal and producing a third signal, an addressinput circuit for receiving address indicating the selection of thememory banks, and a logic circuit responsive to the first, second andthird signals and the address signals including a latch circuitcorresponding to the respective banks for storing data representing theactive cycle for the bank selected by the address and data representingthe precharge cycle for unselected banks.

According to still another aspect of the present invention, a dynamicrandom access memory receiving an external clock includes a plurality ofmemory banks each including a plurality of memory cells and operable ineither an active cycle indicating a read cycle or a write cycle, or aprecharge cycle, a circuit for receiving a row address strobe signal andlatching a logic level of the row address strobe signal in response toone of a rising edge and a falling edge of the clock, an address inputcircuit for receiving an externally generated address selecting one ofthe memory banks, and a circuit for receiving the latched logic levelfrom the receiving and latching circuit and the address from the addressinput circuit and for outputting an activation signal to the memory bankselected by the address and an inactivation signals to unselected memorybanks when the latched logic level is a first logic level, so that theselected memory bank responsive to the activation signal operates in theactive cycle while the unselected memory banks responsive to theinactivation signals operate in the precharge cycle.

According to still another aspect of the present invention, asemiconductor memory formed on a semiconductor chip receiving anexternal clock to the chip and outputting data read out from memorycells via data output buffer circuit, includes a circuit for generatinga burst length signal representing the time interval of output of dataand outputting data in synchronism with the clock via the data outputbuffer circuit during the time interval corresponding to the burstlength signal.

According to further still another aspect of the present invention, asemiconductor memory includes a memory array having a plurality ofmemory cells arranged in rows and columns, a plurality of sub-arraysprovided by partitioning the memory cell array in the row direction,each of the sub-arrays having a plurality of word lines respectivelyconnected to associated columns of the memory cells and a plurality ofbit lines respectively connected to associated rows of the memory cells,the bit lines of each sub-array divided into first groups of bit linesand second groups of bit lines, the respective ones of which are dividedinto first sub-groups of bit lines and second sub-groups of bit lines,the first groups of each sub-array alternately arranged with the secondgroups thereof, the first sub-groups of each sub-array alternatelyarranged with the second sub-groups thereof, and I/O buses respectivelydisposed in parallel to the word lines between the sub-arrays and onouter sides of the sub-arrays, and divided into first I/O buses andsecond I/O buses respectively arranged at odd and even positions, eachI/O bus divided into first I/O lines and second I/O lines, the first andthe second I/O lines of the respective first I/O buses respectivelyconnected via column selection switches with the bit lines of the firstand the second sub-groups of the first groups of sub-arrays adjacentthereto, the first and the second I/O lines of the respective second I/Obuses respectively connected via column selection switches with the bitlines of the first and the second sub-groups of the second groups ofsub-arrays adjacent thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, and advantages of the presentinvention are better understood by reading the following detaileddescription of the invention, taken in conjunction with the accompanyingdrawings, wherein:

FIGS. 1A and 1B show a schematic plane view of various component partsformed on the same semiconductor chip of a synchronous DRAM according tothe present invention;

FIG. 2 is a diagram showing an arrangement relationship with one ofsub-arrays in FIG. 1 and input/output line pairs coupled thereto;

FIG. 3 is a schematic block diagram showing a row control circuitaccording to the present invention;

FIG. 4 is a schematic block diagram showing a column control circuitaccording to the present invention;

FIG. 5A and FIG. 5B are diagrams showing various commands used inoperations of a pulse {overscore (RAS)} and a level {overscore (RAS)},respectively;

FIG. 6 is a schematic circuit diagram showing a clock (CLK) bufferaccording to the present invention;

FIG. 7 is a schematic circuit diagram showing a clock enable (CKE)buffer according to the present invention;

FIG. 8 is an operation timing diagram for the CLK buffer and the CKEbuffer respectively showing in FIG. 6 and FIG. 7;

FIG. 9 is a schematic circuit diagram showing a multifunction pulse{overscore (RAS)} input buffer according to the present invention;

FIG. 10 is a timing diagram for column control signals or clocks used inthe present invention;

FIG. 11 is a schematic circuit diagram for a high frequency clockgenerator for generating multiplied clocks upon precharging according tothe present invention;

FIG. 12 is a schematic circuit diagram for a column address bufferaccording to the present invention;

FIG. 13 is a schematic block diagram for an operation mode settingcircuit according to the present invention;

FIG. 14 is a schematic circuit diagram for a mode set control signalgenerating circuit in FIG. 13;

FIGS. 15A, 15B and 15C are a schematic circuit diagram for an addresscode register in FIG. 13;

FIG. 16 is a schematic circuit diagram for a latency logic circuit inFIG. 13;

FIG. 17 is a schematic circuit diagram for a burst length logic circuitin FIG. 13;

FIG. 18 is a circuit diagram showing an auto-precharge control signalgenerating circuit according to the present invention;

FIG. 19 is a schematic circuit diagram for a row master clock generatingcircuit for generating a row master clock φ_(Ri) according to thepresent invention;

FIG. 20 is a timing diagram showing timing relationship for a mode setand an auto-precharge according to the present invention;

FIG. 21 is a circuit diagram showing a circuit for producing signals toenable the generation of column control signals;

FIG. 22 is an operation timing diagram for the high frequency clockgenerator of FIG. 11;

FIG. 23 is a diagram showing a circuit block diagram on a data pathassociated with one of data buses according to the present invention;

FIG. 24 is a schematic circuit diagram for an I/O precharge andselection circuit according to the present invention;

FIG. 25 is a schematic circuit diagram for a data output multiplexeraccording to the present invention;

FIG. 26 is a schematic circuit diagram for a data output bufferaccording to the present invention;

FIG. 27 is a detail circuit diagram for a data input demultiplexesaccording to the present invention;

FIG. 28 is a schematic circuit diagram for a PIO line driver accordingto the present invention;

FIG. 29 is a schematic circuit diagram for a {overscore (CAS)} bufferaccording to the present invention;

FIG. 30 is a schematic circuit diagram for a {overscore (WE)} bufferaccording to the present invention;

FIG. 31 is a schematic circuit diagram for a DQM buffer according to thepresent invention;

FIG. 32 is a timing diagram showing the operation of the DQM buffer ifFIG. 31;

FIGS. 33A, 33B and 33C are a timing diagram showing a writing operationaccording to the present invention;

FIG. 34 is a schematic circuit diagram for a column address bufferaccording to the present invention;

FIG. 35 is a schematic block diagram for a column address counteraccording to the present invention;

FIG. 36A and 36B are schematic circuit diagram for each stage whichconstitutes a first counting portion in FIG. 35;

FIG. 37 is a timing diagram showing the operation of the circuit of FIG.36A;

FIG. 38 is a schematic block diagram for a column decoder according tothe present invention;

FIG. 39A is a schematic circuit diagram for a first predecoder in FIG.38;

FIG. 39B is a schematic circuit diagram for a second predecoder in FIG.38;

FIG. 40 is a schematic circuit diagram for one of main decoders in FIG.38;

FIGS. 41A, 41B and 41C are a timing diagram showing a reading operationaccording to the present invention;

FIG. 42 and FIG. 43 are schematic circuit diagrams for a burst lengthdetection circuit in FIG. 4;

FIG. 44 is a schematic circuit diagram for a column address reset signalgenerator in FIG. 4;

FIG. 45 is a schematic block diagram for a transfer control counter inFIG. 4;

FIG. 46 is a schematic circuit diagram for a read data transfer clockgenerator in FIG. 4;

FIG. 47 is a schematic circuit diagram showing a circuit for generatinga signal φ_(CL) using in the data output multiplexer of FIG. 25;

FIG. 48 is a schematic circuit diagram for a write data transfer clockgenerator in FIG. 4;

FIGS. 49A49B and 49C are a timing diagram for a {overscore (CAS)}interrupt write operation according to the present invention;

FIG. 50 is a schematic circuit diagram showing a circuit for generatingcontrol signals precharging I/O lines and PIO lines according to thepresent invention;

FIG. 51 is a schematic circuit diagram showing a circuit for generatingcontrol signals precharging DIO lines according to the presentinvention;

FIG. 52 is a schematic circuit diagram showing a circuit for generatingbank selection signals using in the PIO line driver of FIG. 28;

FIG. 53 is a schematic circuit diagram showing a control circuit forgenerating control signals being used in the data output buffer of FIG.26;

FIG. 54, FIG. 55, FIG. 56 and FIG. 57 are timing diagrams showing thetiming relationship according to various operation modes in thesynchronous DRAM using the pulse {overscore (RAS)};

FIG. 58 is a schematic circuit diagram for a {overscore (RAS)} bufferusing in the level {overscore (RAS)};

FIG. 59 is a schematic circuit diagram for a special address bufferaccording to the present invention;

FIG. 60 is a schematic circuit diagram showing a control circuit forgenerating a mode set master clock and a refresh master clock which usein the level {overscore (RAS)};

FIG. 61 is a timing diagram showing the operation timing relationship inthe synchronous DRAM using the level {overscore (RAS)}; and

FIG. 62 is a diagram showing the manner in which the separate sheets ofdrawings of FIG. 1A and FIG. 1B, FIG. 33A to FIG. 33C, FIG. 41A to FIG.41C, and FIG. 49A to FIG. 49C are combined.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention will be discussedreferring to the accompanying drawings. In the drawings, it should benoted that like elements represent like symbols or reference numerals,wherever possible.

In the following description, numerous specific details are set forthsuch as the number of memory cells, memory cell arrays or memory banks,specific voltages, specific circuit elements or parts and so on in orderto provide a thorough understanding of the present invention. It will beobvious to those skilled in the art that the invention may be practicedwithout these specific details.

The synchronous DRAM in its presently preferred embodiment is fabricatedemploying a twin well CMOS technology and uses n-channel MOS transistorshaving a threshold voltage of 0.6 to 0.651, volts, p-channel MOStransistors having a threshold voltage of −0.8 to −0.85 volts and powersupply voltage Vcc of approximately 3.3 volts.

CHIP ARCHITECTURE

Referring to FIG. 1 comprising FIG. 1A and FIG. 1B, illustration is madeon a schematic plane view for various element portions formed on thesame semiconductor chip of a synchronous DRAM according to the presentinvention. The DRAM in the present embodiment is a 16,777,216 bit(16-Mbit) synchronous DRAM made up of 2,097,152 (2M)×8 bits. Memory cellarrays are partitioned into a first bank 12 and a second bank 14, asrespectively shown in FIG. 1A and FIG. 1B, in order to increase a datatransfer rate. Each bank comprises an upper memory cell array 16T and alower memory cell array 16B respectively positioned at upper and lowerportions, each of which contains memory cells of 4,194,304 bits(4-Mbit). The upper and the lower memory cell arrays are respectivelydivided into left memory cell arrays 20TL and 20BL and right memory cellarrays 20TR and 20BR of 2-Mbit memory cells each, neighboring on theirlateral sides. The left and the right memory cell arrays of the uppermemory cell array 16T of each bank will be respectively referred to as aupper left memory cell array or a first memory cell array 20TL and aupper right memory cell array or a third memory cell array 20TR.Likewise, the left and the right memory cell arrays of the lower memorycell array 16B of each bank will be respectively referred to as a lowerleft memory cell array or a fourth memory cell array 20BR. Thus, eachbank is divided into four memory cell arrays consisting of the first tothe fourth memory cell arrays. The upper left and right memory cellarrays and the lower left and right memory cell arrays are respectivelydivided into 8 upper left submemory cell arrays (or upper leftsub-arrays) 2TL1 to 22TL8, 8 upper right submemory cell arrays (or upperright sub-arrays) 22TR1 to 22TR8 and 8 lower right submemory cell arrays(or lower right sub-arrays) 22BR1 to 22BR8. Each of the sub-arrays has256 K-bit memory cells arranged in a matrix form of 256 rows and 1,024columns. Each memory cell is of a known one-transistor one-capacitortype.

In each bank, a row decoder 18 is arranged between the upper memory cellarray 16T and the lower memory cell array 16B. The row decoder 18 ofeach bank is connected with 256 row lines (word lines) of eachsub-array. Word lines of respective one of the upper and the lowersub-array pairs 22TL1, 22BL1; 22TL2, 22BL2; . . . ; 22TR8, 22BR8arranged in a symmetrical relationship with respect to the row decoder18 are extending in opposite directions therefrom in parallel with avertical direction. The row decoder 18 responsive to row addresses froma row address buffer selects one of sub-arrays and one of word lines ofthe respectively selected sub-arrays and provides a row drivingpotential on each selected word line. Thus, in response to given rowaddresses in each bank, the row decoder 18 selects total four wordlines: one word line selected in a selected one of the upper leftsub-arrays 22TL1-22TL8, one word line selected in a selected one of thelower left sub-arrays 22BL1-22BL8, one word line selected in a selectedone of the upper right sub-arrays 22TR1-22TR8 and one word line selectedin a selected one of the lower right sub-arrays 22BR1-22BR8.

Column decoders 24 are respectively positioned adjacent to right sideends of the upper and the lower memory cell arrays 16T and 16B in thefirst bank 12 and to left side ends of the upper and lower memory cellarrays 16T and 16B in the second bank 14. Each of the column decoders 24is connected to 256 column selection lines which are parallel in thehorizontal direction and perpendicular to the word lines, serving asselecting one of the column selection lines in response to a columnaddress.

I/O buses 26 are located adjacent to both side ends of the respectivesub-arrays 22TL, 22BL, 22TR and 22BR, extending in parallel with theword lines. The I/O buses 26 between opposite side ends of sub-arraysare shared by these two adjacent sub-arrays. Each of the I/O buses 26 iscomposed of our pairs of I/O lines, each pair of which consists of twosignal lines in the complementary relation and is connected withcorresponding bit line pair via a column selection switch and a senseamplifier.

Referring now to FIG. 2, for purposes of simplicity, the drawing isrepresented which illustrates the arrangement of an odd numbered one ofsub-arrays 22TL1 to 22TR8 in the upper memory cell array 16T and that ofI/O buses associated therewith. A first or left I/O bus 26L and a secondor right I/O bus 26R respectively run in parallel with wordlinesWL0-WL255 at left and right ends of the sub-array 22. Each of the firstand the second I/O buses 26L and 26R consists of first I/O line pairswhich are composed of I/O line pairs I/O0, {overscore (I/O0)} and I/O1,{overscore (I/O1)}, and second I/o line pairs which are composed of I/Oline pairs I/O2, {overscore (I/O2)} and I/O3, {overscore (I/O3)}. Thesub-array 22 contains 1,024 bit line pairs 28 perpendicular to the wordlines WL0-WL255 which are arranged in a folded bit line fashion. Memorycells 30 are located at crosspoints of word lines and bit lines. The bitline pairs 28 constituting the sub-array 22 are divided into a pluralityof first bit line groups 28L1 to 28L256 arranged at odd locations and aplurality of second bit line groups 28T1 to 28T256 arranged at evenlocations. Each of the bit line groups has a given number of bit linepairs (2 bit line pairs in the present embodiment). The first bit linegroups 28L are arranged to alternate with the second bit line groups28R. Odd numbered bit line pairs (or first sub-groups) 28L1, 28L3, . . ., 28L255 and even numbered bit line pairs (or second sub-groups) 28L2,28L4, . . . , 28L256 of the first bit line groups 28L are respectivelyconnected with the first I/O line pairs and the second I/O line pairs ofthe first I/O bus 26L via corresponding sense amplifiers 32L and columnselection switches 34L. In the same manner, odd numbered bit line pairs(or first sub-groups) 28T1, 28T3, . . . , 28T255 and even numbered bitline pairs (or second sub-groups) 28T2, 28T4, . . . , 28T256 of thesecond bit line groups 28R are respectively connected with the first I/Oline pairs and the second I/O line pairs of the second I/O bus 28R viacorresponding amplifiers 32R and column selection switches 34R. Firstcolumn selection lines L0, L2, . . . and L254, which are connected withcolumn selection switches associated with the first I/O line pairs I/O0,{overscore (I/O0)} and I/O1, {overscore (I/O1)} in left and right I/Obuses 26L and 26R, are arranged in parallel to alternate with secondcolumn selection lines L1, L3, . . . and L255 which are connected tocolumn selection switches associated with the second I/O line pairsI/O2, {overscore (I/O2)} and I/O3, {overscore (I/O3)} therein. Thus, ina read operation, after the selection of one word line, i.e., one pagewith row addresses, the first and the second I/O line pairs in the leftand right I/O buses 26L and 26R provide continuous data, alternatingdata of two bits each by sequentially selecting column selection linesL0 to L255. Line pairs 36, which are connected with corresponding senseamplifiers 32L and 32R and are alternately running in oppositedirections, are respectively connected with corresponding bit linegroups 28L and 28R via corresponding sense amplifiers within sub-arraysadjacent to the first and second I/O buses 26L and 26R. That is, thefirst I/O line pairs and the second I/O line pairs of the first I/O bus26L are respectively connected with odd numbered bit line pairs (orfirst sub-groups) and even numbered bit line pairs (or secondsub-groups) of the first bit line groups of a left adjacent sub-array(not shown) via corresponding column selection switches 32L andcorresponding sense amplifiers. In the same manner, the first I/O linepairs and the second I/O line pairs of the second I/O bus 26R arerespectively connected with odd numbered bit line pairs (or firstsub-groups) and even numbered bit line pairs (or second sub-groups) ofthe second bit line groups of a right adjacent sub-array (not shown) viacorresponding column selection switches 32R and corresponding senseamplifiers. Thus, since bit line pairs of the respective sub-arrays aredivided in the same manner as the first and second bit line groups ofthe sub-array 22 as shown in FIG. 2, I/O buses associated with the firstbit line groups are alternately arranged with I/O buses associated withthe second bit line groups. That is, each of first I/O buses positionedat odd locations is associated with the first bit line groups in twosub-arrays adjacent thereto while each of second I/O buses positioned ateven locations is associated with the second bit line groups in twosub-arrays adjacent thereto. Regarding to the respective ones of thesub-arrays of FIG. 1, the connection relationship with the first andsecond I/O line pairs of the first and second I/O buses will beincorporated by the explanation made in connection with FIG. 2. Thesense amplifier 32L and 32R may be of a known circuit which is composedof a P-channel sense amplifier, transfer transistors for isolation, anN-channel sense amplifier and an equalizing and precharging circuit.Thus, I/O buses 26 between adjacent two sub-arrays are common I/O busesfor reading or writing data from/to the sub-array which is selected bythe control of the isolation transfer transistors.

Returning to FIG. 1, in each bank, at the upper portion of the first andthe third memory cell arrays 20TL and 20TR are respectively located I/Oline selection and precharge circuits 38TL and 38TR and I/O senseamplifiers and line drivers 40TL and 40TR correspondingly connected,thereto, and likewise, at the lower portion of the second and the fourthmemory cell arrays 20BL and 20BR are respectively located I/O lineselection and precharge circuits 38BL and 38BR and I/O sense amplifiersand line drivers 40BL and 40BR correspondingly connected thereto. I/Oline selection and precharge circuits 38TL, 38TR, 38BL and 38BR arerespectively connected to alternating I/O buses 26 in correspondingmemory cell arrays 20TL, 20TR, 20BL and 20BR. That is, I/O lineselection and precharge circuits positioned at odd locations arerespectively connected with I/O bus pairs of I/O buses disposed at oddlocations in corresponding memory cell arrays, and I/O line selectionand precharge circuits positioned at even locations are respectivelyconnected with I/O bus pairs of even located I/O buses in correspondingmemory cell arrays. Therefore, in each bank, each of circuits at theouter most side of the I/O line selection and precharge circuits mayaccess data to/from memory cells which are connected with first bit linegroups in three sub-arrays, and odd positioned I/O line selection andprecharge circuits and even positioned I/O line selection and prechargecircuits, which are excluding the outer most I/O line selection andprecharge circuits, are respectively associated with the first bit linegroups and the second bit line groups. Each I/O line selection andprecharge circuit 38 comprises an I/O bus selection circuit forselecting one of a pair of I/O buses connected thereto and an I/O lineprecharge circuit for precharging, when any one of first I/O line pairsI/O0, {overscore (I/O0)} and I/O1, {overscore (I/O0)} and second I/Oline pairs I/O2, I/O2 and I/O3, {overscore (I/O3)} which constitute theselected I/O bus is transferring data, the other I/O line pairs.

I/O line selection and precharge circuits 38 are respectively connectedto corresponding I/O sense amplifiers and line drivers 40 via PIO buses44. Each PIO bus 44 is connected with an I/O bus selected bycorresponding I/O bus selection circuit. Thus, PIO buses 44 comprisefour pairs of PIO lines like I/O buses 26. Each I/O sense amplifier andline driver 40 comprises an I/O sense amplifier for amplifying datainputting via corresponding I/O bus selection circuit and PIO bus in aread operation, and a line driver for driving to an I/O bus selected bythe I/O bus selection circuit data inputting via corresponding I/O busselection circuit and PIO bus in a write operation. Thus, as discussedabove, if data on any ones of the first and the second I/O line pairsinputs to the sense amplifier via corresponding PIO line pairs, PIO linepairs connected to the other I/O line pairs are precharged together withthe I/O line pairs. Also, in the writing operation, when the driver 40drives data to corresponding I/O line pairs via selected PIO line pairs,unselected PIO line pairs and their corresponding I/O line pairs startprecharging.

At the upper most and the lower most ends of the synchronous DRAM chip,upper data buses 42T and lower data buses 42B are respectively runningin parallel with the horizontal direction. Each of upper data buses 42Tand lower data buses 42B consist of four data buses, each of whichcomprises four pairs of data lines which are the same number as abovementioned I/O bus and PIO bus. One side ends of four data buses DBO-DB3constituting upper data buses 42T and four data buses DB4-DB7constituting lower data buses are respectively connected to datainput/output multiplexers 46 coupled to input/output pads (not shown inthe drawing) via input/output lines 47 and data input/output buffers 48.

In each bank, I/O sense amplifiers and line drivers 40TL associated withthe first memory cell array 20TL are alternately connected to first andsecond data buses DB0 and DB1, and I/O sense amplifiers and line drivers40TR associated with the third memory cell array 20TR are interleavelyconnected to third and fourth data buses DB2 and DB3. Likewise, I/Osense amplifiers and line drivers 40BL associated with the second memorycell array 20BL are interleavely connected to fifth and sixth data busesDB4 and DB5, and I/O sense amplifiers and line drivers 40BR associatedwith the fourth memory cell array 20BR are interleavely connected toseventh and eighth data buses. Center I/O sense amplifiers and linedrivers 43T and 43B are respectively connected to I/O buses between thefirst memory cell array 20TL and the third memory cell array 20TR andbetween the second memory cell array 20BL and the fourth memory cellarray 20BR in each bank. In each bank, center I/O sense amplifier andline driver 43T at the upper portion comprises an I/O sense amplifierfor amplifying data on corresponding I/O bus to couple to the data busDB1 or DB3 in response to a control signal in a write operation. Likely,center I/O sense amplifier and line driver 43 at the lower portion isconnected to the fourth and the eighth data buses DB5 and DB7.

Now, assuming that sub-arrays 22TL3, 22BL3, 22TR3 and 22BR3 in the firstbank 12 and one word line in their respective sub-arrays would beselected by the row decoder 18 responded by a row address, the rowdecoder 18 provides block information signals designating respectivesub-arrays 22TL3, 22BL3, 22TR3 and 22BR3. Then, in a read operation, acontrol circuit, as will be discussed hereinbelow, generates sequentialcolumn addresses in response to an external column address and thecolumn decoder 24 generates sequential column selection signals inresponse to this column address stream. Assuming that the first columnselection signal is to select a column selection line L0, correspondingcolumn selection switch 34 shown in FIG. 2 is turned on and datadeveloped on corresponding bit line pairs is transferred to first I/Oline pairs I/O0, {overscore (I/O0)} and I/O1, {overscore (I/O1)} of leftand right I/O buses arranged at both ends of the respective selectedsub-arrays. I/O line selection and precharge circuits 38TL, 38BL, 38TRand 38BR respond to the block information signals, and I/O lineselection and precharge circuits associated with the selected sub-arrays22TL3, 22B13, 22TR3 and 22BR3 thereby select the left and the right I/Obuses associated therewith. Data on the first I/O line pairs in the leftand the right I/O buses is transferred to corresponding data line pairsin corresponding data buses DB0-DB7 via corresponding PIO line pairs andcorresponding sense amplifiers turned on by a control signal which isgenerated in response to the block information signals. However, at thistime, I/O line pairs not transferring data, i.e., the second I/O linepairs and PIO line pairs connected thereto are all held in a prechargingstate by the I/O precharge circuits. Also, data line pairs nottransferring data are being precharged by data input/output multiplexers46 as will be explained hereinbelow. Then, if by the second columnselection signal CSL1 on the column line L1 of the column address streamare turned on corresponding column selection switches, in the samemanner as preciously discussed, data on corresponding bit lies istransferred via the second I/O line pairs in the left and the right I/Obuses and corresponding PIO line pairs to data line pairs, whereas thefirst I/O line pairs, PIO line pairs and data line pairs connectedthereto are precharged to transfer data from now on. If column selectionsignals CSL2 to CSL255 on column lines L2 to L255 following the columnselection signal CSL1 on the column line L1 are sequentially received,the same operations as data transfer operations in case of the columnselection signals CSL0 and CSL1 are performed repetitively. Thus, alldata on bit line pairs which is developed from all memory cells coupledto selected word lines can be read out. That is, full page read-out isavailable. In the read operation, the first I/O line pairs and thesecond I/O line pairs transfer a plurality of data, alternating datatransfer and precharge, and the first and the second data line pairsassociated with the first and the second I/O line pairs, also, repeatdata transfer and precharge periodically. The data output multiplexerconnected to each data bus not only stores a plurality of datatransferred in parallel via any one of the first and the second dataline pairs, but also precharges the other data line pairs. Thus, eachdata output multiplexer provides continuous serial data in response todata selection signals, prefetching a plurality of data on the first andthe second data line pairs with a predetermined period. The serial dataoutputs via corresponding data output buffer to data input/output padsin synchronism with a system clock. Therefore, 8-bit parallel datacontinuously outputs every clock cycle thereof.

Write operation is performed in the inverse order of the read operationas discussed above. As will be explained in brief, serial input dataoutputs in synchronism with the system clock from data input buffers viadata interleavely pads. The serial data from the data input buffers isinterleavely transferred to the first and the second data line pairs ofcorresponding data buses in a plurality of parallel data every clockcycles of the system clock by means of respective data inputdemultiplexers. Data on the first and the second data line pairs issequentially written into selected memory cells via corresponding linedrivers, I/O buses selected by the I/O line selection circuits andcorresponding bit line pairs. Data transfer and precharge of the firstand the second line pairs are alternately effected every clock cycles inthe same manner as those in the read operation.

Between the first and the second banks is arranged the control circuit50 for controlling operations of the synchronous DRAM according to thepresent invention. The control circuit 50 serves to generate controlclocks or signals for controlling the row and the column decoders 18 and24, I/O line selection and precharge circuits 38, I/O sense amplifiersand line drivers 40 and 43, data input/output multiplexers 46 and datainput/output buffers 48. The control circuit 50 may be classified into arow control circuit and a column control circuit. The row controlcircuit, the data path and the column control circuit will be separatelydiscussed hereinbelow.

Row Control Circuit

Conventional DRAMs are activated to perform the operation of read, writeor the like by a logic level of {overscore (RAS)}, for example, a lowlevel. This will be referred to as a level {overscore (RAS)}. The level{overscore (RAS)} gives a certain information, for example, suchinformation as the transition of {overscore (RAS)} from high to lowlevel indicates the activation thereof and the transition of {overscore(RAS)} from low to high level indicates precharging. However, since thesynchronous DRAM has to operate in synchronism with the system clock,above-mentioned commands using in the conventional DRAM cannot beemployed in the synchronous DRAM. That is, since the synchronous DRAMneeds to sample a command information at the leading edge or the fallingedge of the system clock (sampling the command information in thisembodiment is accomplished at the leading edge thereof), even if thelevel{overscore (RAS)} is applied in the synchronous DRAM, commands ofthe conventional level {overscore (RAS)} cannot be used therein.

FIG. 5A and FIG. 5B are timing diagrams representative of commands usedin the synchronous DRAM of the present invention. FIG. 5a representsvarious commands in case that {overscore (RAS)} signal of pulse(hereinafter referred to as a pulse {overscore (RAS)}) is used, and FIG.5b various commands in case of the use of level {overscore (RAS)}. Ascan be seen in the drawings, when {overscore (RAS)} is low and{overscore (CAS)} signal and write enable signal {overscore (WE)} arehigh at the leading edge of the system clock CLK, this means anactivation. After the activation, at the leading edge of the systemclock, the high level {overscore (RAS)}, the low level {overscore (CAS)}and the high level {overscore (WE)} indicate a read command. Also, afteractivation, at the leading edge of the system clock CLK, the high level{overscore (RAS)}, the low level {overscore (CAS)} and low level{overscore (WE)} represent a write command. When the low level{overscore (RAS)}, the high level {overscore (CAS)} and the low level{overscore (WE)} have been sampled at the leading edge of the clock CLK,a precharging operation is performed. An establishment of operation modeset command according to the feature of the present invention isaccomplished at low levels of {overscore (RAS)}, {overscore (CAS)} and{overscore (WE)} at the leading edge of the clock CLK. A {overscore(RAS)}-before-{overscore (RAS)} (CBR) refresh command inputs when{overscore (RAS)} and {overscore (CAS)} hold at low levels and{overscore (WE)} holds at a high level at the leading edge of the clockCLK. A self refresh command, which is a variation of the CBR refresh,inputs when {overscore (RAS)} and {overscore (CAS)} line at low levelsand {overscore (WE)} stays at a high level at successive three leadingedges of the clock CLK.

In the same manner as conventional DRAM, the synchronous DRAM, also,inherently has the time period from the activation of {overscore (RAS)}until the activation of {overscore (CAS)}, i.e. {overscore(RAS)}-{overscore (CAS)} delay time t_(RCD) and the precharging timeperiod prior to the activation of {overscore (RAS)}, i.e. {overscore(RAS)} precharge time t_(RP). To guarantee the read-out and the write-inof valid data, minimum values of tRCD and t_(RP) (respectively 20 ns and30 ns in the synchronous DRAM of the present invention) are veryimportant to memory system designers. To promote the convenience forsystem designers, it may be more preferred that the minimum values oft_(RCD) and t_(RP) are provided in the number of system clock cycle. Forexample, in case that the system clock frequency is 100 MHZ and theminimum values of t_(RCD) and t_(RP) are respectively 20 ns and 30 ns,clock cycles of t_(RCD) and t_(RP) respectively become 2 and 3. The rowcontrol circuit is means for generating signals or clocks for selectingword lines during the time period of t_(RCD), developing to bit linesinformation data from memory cells in a read operation and prechargingduring the time period of t_(RP).

FIG. 3 is a diagram representing a schematic block diagram forgenerating row control clocks or signals. Referring to the drawing, aclock buffer (hereinafter referred to a CLK buffer) 52 is a buffer forconverting into an internal system clock φ_(CLK) of CMOS level inrespective to an external system clock CLX of TTL levee The synchronousDRAM executes various internal operations which are sampling signalsfrom the external chip or data to the external chip at the leading edgeof the clock CLK. The CLK buffer 52 generates a clock CLK faster thanthe phase of the clock CLK in response to CLK.

A clock enable (CKE) buffer 54 is a circuit for generating a clockmasking signal φ_(CKE) in order to make the generation of the clockφ_(CLK) in response to an external clock enable signal CKE and the clockCLK. As will be discussed hereinbelow, the internal system clock φ_(CLK)disabled by the signal φ_(CKE) causes the internal operation of the chipto be frozen and input and output of data is thereby blocked.

A {overscore (RAS)} buffer 56 receives the external signal {overscore(RAS)}, address signals SRA10 and SRA11, a signal φ_(c) from a{overscore (CAS)} buffer and a signal φ_(WRC) from a {overscore (WE)}buffer, thereby generating {overscore (RAS)} clock φ_(RCi) forselectively activating banks in synchronous with the clock φ_(CLK),selectively or totally precharging the banks and automaticallyprecharging after refreshing or operation mode programming. Wherein i isa symbol for representing bank. Also, the {overscore (RAS)} buffer 56generates signal φ_(RP) which represents the activation of {overscore(RAS)} with the clock φ_(CLK).

An operation mode set circuit 58 is responsive to the operation mode setcommand, signals φ_(RP), φ_(c) and φ_(WRC) and address signals RA0-RA6fso as to set various operation modes, for example, operation modes forestablishing a {overscore (CAS)} latency, a burst length representingthe number of continuous output data and an address mode φ_(INTEL)representing a scrambling way of internal column address. The operationmode set circuit 58 sets a default operation mode in which predetermined{overscore (CAS)} latency, burst length and address mode areautomatically selected upon the absence of the operation mode setcommand.

A row master clock generator 62 is responsive to the control signalφ_(RCi) and a latency signal CLj and generates a row master clock φ_(Ri)which is based on the generation of clocks or signals associated with{overscore (RAS)} chain in a selected bank. According to thecharacteristics of the present invention, the row master clock φ_(Ri)has time a delay depending on a designated {overscore (CAS)} latency andsuch a time delay guarantees 2-bit data output synchronous to the systemclock after the precharge command.

A row address buffer 60 receives the row master clock φ_(Ri), externaladdress signals A0-A11 and a row address reset signal φ_(RARi) togenerate row address signals RA0-RA11 in synchronism with the clockφ_(CLK). The buffer 60 receive a count signal from a refresh counter ina refresh operation to provide row address signals RA0-RA11 forrefreshing.

A row control signal generator 64 receives the row master clock φ_(Ri)and a block information signal BLS from the row decoder 18 to generate aboosted word line driving signal φ_(X), a sensing start signal φ_(S) foractivating the selected sense amplifier, a row address reset signalφ_(RARi) for resetting the column address buffer, a signal φ_(RALi) forpowering on the row address buffer 60 and a signal φ_(RCDi) forinforming the completion of clocks or signals associated with rows.

A column enable clock generator 66 receives the signal φ_(RCDi) and therow master clock φ_(Ri) to generate signals φ_(YECi) and φ_(YEi) forenabling column related circuits.

A high frequency clock generator 68 generates, in case that thefrequency of the external system clock CLK is low and the 2-bit dataoutput is also required in a read operation after a precharge command, aclock CNTCLK9 with a higher frequency than the clock CLK to prevent thereduction of precharge period. As will be discussed hereinbelow, sincethe column address generator generates column addresses with the clockCNTCLK9, the reduction of precharge period is prevented.

Hereinbelow, explanation will be made in detail on preferred embodimentsof elements constituting the {overscore (RAS)} chain clock generator.

1. CLK Buffer & CKE Buffer

FIG. 6 is a diagram representing a schematic circuit diagram for the CLKbuffer 52 according to the present invention, and FIG. 7 is a schematiccircuit diagram for CKE buffer 54 according to the present invention.FIG. 8 depicts an operation timing diagram for the CLK buffer 52 and theCKE buffer 54.

Referring to FIG. 6, a differential amplifier 70 compares the externalsystem clock CLK with a reference potential V_(REF) (=1.8 volts) andthereby converts the external signal CLK of TTL level into an internalsignal of CMOS level, for example, a high level of 3 volts or a lowlevel of 0 volt. Instead of the differential amplifier 70, another inputbuffers can be used which can level shift from the TTL to the CMOSsignal. As can be seen in FIG. 8, the clock CLKA is of the signalinverted to the system clock CLK via the input buffer 70, such as thedifferential amplifier, and gates, i.e., inverters 76 and NAND gate 78.A flip-flop or a latch 80 which is composed of NOR gates 72 and 74outputs a system clock of CMOS level when a clock masking signal φ_(CKE)is low. The output clock from the flip-flop 80 is supplied to a pulsewidth adjusting circuit 85 which is composed of a delay circuit 82 and aNAND gate 84. Although the delay circuit 82 illustrates only invertersfor the purpose of simplicity, a circuit comprising inverter andcapacitor or other delay circuits may be used. Thus, when the signalφ_(CKE) is low, the internal system clock φ_(CLK) as shown in FIG. 8outputs from the CLK buffer. However, when the signal φ_(CKE) is high,the output of the flip-flop 80 becomes low thereby to stop thegeneration of the clock φ_(CLK). In FIG. 6, inverter 89, p-channel MOStransistor 90 and n-channel MOS transistors 91 and 94 are elements forproviding an initial condition to proper nodes in response to a power-on(or power-up) signal φ_(VCCH) from a known power-on circuit. Thepower-on signal φ_(VCCH) maintains a low level until the power supplyvoltage Vcc reaches a sufficient level after the application of thesupply voltage.

Referring to FIG. 7, input buffer 70 converts the external clock enablesignal CKE into a CMOS level signal. To prevent power consumption,operation of the input buffer 70 is inhibited by a self-refreshoperation. The input buffer 70 provides an inverted CMOS level signal ofthe signal CKE on a line 90. The inverted CKE signal is coupled to ashift register 86 for shifting with an inverted clock CLKA of the clockCLK. The output of the shift register 86 is coupled to the outputterminal of the signal φ_(CKE) via a flip-flop 88 of NOR type and aninverter. The output terminal of the shift register 86 is coupled to theoutput terminal of a signal. CKEBPU via inverters.

The clock enable signal CKE is of inhibiting the generation of thesystem clock φ_(CLK) with a low level of CKE, thereby to freeze theinternal operation of the chip. Referring again to FIG. 8, illustrationis made on the signal CKE with a low level pulse for masking the CLKclock 98. By the low level of CKE, the input line 90 of the shiftregister 86 maintains a high level. After a CLKA clock 100 goes to a lowlevel, the output of the shift register 86 goes to a high level. Thus,φ_(CKE) and CKEBPU become a high level and a low level, respectively.Then, after a next CLKA clock 102 goes to a low level, the output of theshift register 86 changes to a low level, thereby causing the signalCKEBPU to go high. At this time, since the output of the flip-flop 88 iskeeping a low level, φ_(CKE) maintains a high level. However, after anext CLKA clock 104 goes to a high level, φ_(CKE) goes to a low level.Thus, as discussed with FIG. 6, φ_(CLK) clock corresponding to the clock98 is masked with the high level of φ_(CKE)

Since the internal operation of the synchronous DRAM operates insynchronism with the clock φ_(CLK), the masking of φ_(CLK) causes theinternal operation to be in a standby state. Thus, to prevent powerconsumption in the standby state, the signal CKEBPU is used to disableinput buffers synchronous to φ_(CLK). Accordingly, it should beappreciated that the signal CKE needs to be applied prior to at leastone cycle of the masked clock CLK in order to mask it and has to hold ahigh level in order to carry out a normal operation.

2. {overscore (RAS)} Buffer

The synchronous DRAM includes two memory banks 12 and 14 on the samechip to achieve a high speed data transfer rate. To achieve a highperformance of the synchronous DRAM, control circuits need which isselectively controlling various operations for each bank. Accordingly,the {overscore (RAS)} buffer is an input buffer combined withmultifunctions according to a feature of the present invention.

FIG. 9 is a schematic circuit diagram showing the multifunction pulse{overscore (RAS)} input buffer 56 according to the present invention.Referring to FIG. 9, in the same manner as above discussed inputbuffers, input buffer 70 converts an external row address strobe signal{overscore (RAS)} into an internal CMOS level signal. The input buffer70 is disabled by a gate circuit 106 for gating system clock masking,self-refresh and power-on signals CKEBPU, φ_(VCCH) and φ_(SELF). TheCMOS level signal from the input buffer 70 is supplied to an inputterminal 110 of a synchronization circuit 108 for providing to an outputterminal 112 the {overscore (RAS)} pulse φ_(RP) which synchronizes theCMOS level signal to the internal system clock φ_(CLK). Thus, as shownin FIG. 10, at times t₁ and t₃, {overscore (RAS)} being at low levelsgenerates a {overscore (RAS)} pulse φ_(RP) with high levels after apredetermined delay at the output terminal 112.

In FIG. 9, the remaining circuit excluding the input buffer 70, thesynchronization circuit 108 and the gate circuit 106 is a multifunctioncontrol circuit 114 combined therewith to control the respective banks.Since n-channel transistors 148 and 150 are all turned on by φ_(VCCH)being at a low level during the power-on operation, the first {overscore(RAS)} clock φ_(RC1) for the first bank 12 and the second {overscore(RAS)} clock φ_(RC2) for the second bank 14 are all latched in initialconditions, i.e., low levels by means of latches 154 and 156.

To activate the first bank 12 and at the same time, to inactivate thesecond bank 14, at a time t₁ as shown in FIG. 10, external addresssignal ADD with address A₁₁ being at a low level is supplied to thechip. Then, an address buffer, as will be discussed hereinbelow,generates an address signal SRA11 of a low level ({overscore (SRA11)} ofa high level) with the address signal ADD. On the other hand, at thetime t₁, since both {overscore (CAS)} and {overscore (WE)} keep highlevels, φ_(c) and φ_(WRC) hold low levels as will be discussedhereinbelow. Thus, NOR gates 116 and 126 output low levels and NANDgates 122 and 124 output high levels. Then, NAND gates 128 and 130output a high level and a low level, respectively. When the pulse φ_(RP)goes to a high level, NAND gate 132 goes to a low level and NAND gates134 to 138 go to high levels. Then, p-channel transistor 140 is turnedon and p-channel transistor 144 and n-channel transistors 142 and 146keep off states. Thus, latch 54 stores a low level. On the other hand,when φ_(RP) goes to a low level, all of NAND gates 132 to 138 go to highlevels, thereby turning off transistors 140 to 146. As a result, thefirst {overscore (RAS)} clock φ_(RC2) maintains a low level by means ofthe latch 156 which had been initially storing the high level. Thus, thefirst bank 12 is activated by the clock φ_(RC1), thereby performing anormal operation such as a read or a write operation. However, thesecond bank 14 is not activated by the low level clock φ_(RC2).

On the other hand, to access the synchronous DRAM at a high transferrate, the second bank can be activated during the activation of thefirst bank. It can be accomplished by activating the second bank,applying the address A₁₁ being at a high level after the activation ofthe first bank. Then, the address signal SRA11 becomes a high level({overscore (SRA11)} becomes a low level). In the same manner asdiscussed above, NAND gate 136 outputs a low level and all of NAND gates132, 134 and 138 output high levels. Thus, φ_(RC1) is maintaining theprevious state, i.e., the high level and φ_(RC2) goes to a high level.As a result, all of the first and the second banks stay in activationstates.

During the read or the write operation of the second banks, the firstbank may also be precharged. When or before the precharge command isissued at time t₃ as shown in FIG. 10, external address signal A₁₀ andA₁₁, which are all low levels, are applied to corresponding address pinsof the chip. Then, address signals SRA10 and SRA11 become low levels({overscore (SRA11)} becomes a high level). After the command, φ_(RP)and φWRC go to high levels and φ_(c) is at a low level. Consequently,when φ_(RP) goes high, NAND gate 134 goes to a low level and all of NANDgates 132, 136 and 138 maintain high levels. Thus, the transistor 142 isturned on an transistors 140, 144 and 146 maintain off states. The latch154 stores a high level and φ_(RC1) becomes a low level. However,φ_(RC2) maintains the previous state of the high level by means of thelatch 156. As a result, φ_(RC1) of the low level causes the first bankto be precharged during performing data access from the second bank 14.Likewise, a precharge operation of the second bank may be accomplishedby applying the precharge command, address signal A₁₀ being at a lowlevel and address signal A₁₁ being at a high level.

On the other hand, a simultaneous precharge operation of both the firstand the second bank 12 and 14 may be accomplished by applying theprecharge command and an address A₁₀ being at a high irrespective of alogic level of the address A₁₁. Then, in the same manner as discussedabove, NAND gates 134 and 138 output low levels and NAND gates 132 and136 output high levels. Thus, transistors 142 and 146 are turned on andtransistors 140 and 144 maintain off states. As a result, latches 154and 156 store precharge information being at high levels, respectivelyand both φ_(RC1) and φ_(RC2) become low levels.

A CBR refresh command is issued by {overscore (RAS)} being at the lowlevel and {overscore (CAS)} being at the high level as shown in FIG. 5A.Thus, the high level signal φ_(c) and the low level signal φ_(WRC) inputto the multifunction control circuit 114. In this case, NAND gate 124and NOR gate 126 output low levels irrespective of logic levels of theaddress A₁₀ and A₁₁. Consequently, NAND gates 132 and 136 output lowlevels and NAND gates 134 and 138 output high levels. Thus, transistors140 and 144 are turned on and transistors 142 and 146 are turned off.Then, φ_(RC1) and φ_(RC2) become high levels and both banks therebyperform the CBR refresh operation. On the other hand, a selective CBRrefresh operation for both banks can be accomplished by grounding one oftwo input terminals of NAND gate 124. Then, in the same manner asdiscussed above, φ_(RC1) and φ_(RC2) can be selectively enabledaccording to a logic state of the address A₁₁. That is, a low leveladdress A₁₁ under the CBR refresh command causes only the first bank tobe refreshed.

3. Row Address Buffer

FIG. 12 is a diagram showing a schematic circuit diagram from the rowaddress buffer 60 according to the present invention. In the drawing, aninput buffer 70 converts input address signal AI (I=0, 1, 2, . . . , 11)to address signal of CMOS level in the same way as discussed inconnection with above-mentioned input buffers. A logic circuit 158 forgenerating a control signal RABPU to enable or disable the input buffer70 is also illustrated in FIG. 12. The control signal RABPU becomes ahigh level when both banks have activated or the system lock maskingoperation as enabled or the refresh operation has initiated, and theinput buffer 70 is thereby disabled to prevent power consumption.Between the output terminal 161 of the input buffer 70 and a node 162 isconnected a tristate inverter 160. The inverter 160 lies in an off stateby the refresh signal O_(RFH) being at a low level during the refreshoperation. In a normal operation such as a read or a write operation,the inverter 160 outputs a row address signal synchronized with theinternal system clock φ_(CLK). The row address signal is stored in alatch 164. A plurality of row address providing circuits, the number ofwhich is determined by that of banks, are connected to a node 166. Sincetwo banks is used in the embodiment of the present invention, it shouldbe appreciated that two row address providing circuits 168 and 170 areconnected in parallel to the node 166. The row address providing circuit168 for the first bank 12 is comprised of a NOR gate 174, inverters 176and 180, a transmission gate 172, a latch 178 and NAND gates 182 and184. The row address providing circuit 170 for the second bank 14 hasthe same construction as the row address providing circuit 168. Arefresh address providing circuit 198 is connected to the circuits 168and 170 and serves to supply to the row address providing circuits 168and 170 a count value RCNTI from a refresh counter (not shown) in therefresh operation.

It is assumed that the first bank 12 was in inactive state while thesecond bank 14 was in normal state such as a read or a write operation.In this case, a first bank row master clock φ_(R1) and a first bank rowaddress reset signal φ_(RAR1) would be at low levels, and a second bankrow master clock φ_(R2) and a second bank row address reset signalφ_(RAR2) would be at high levels. It is now further assumed that thefirst bank 12 is activated at a time t₁ as illustrated in FIG. 10. Thenbefore the clock φ_(R1) goes to a high level, a row address from theexternal pin AI is stored in the latch 164 as previously described andthe stored row address is then stored into the latch 178 via thetransmission gate 172 turned on by low level signals of φ_(R1) andφ_(RAR1). However, in this case, since the clock φ_(R2) continuouslyremains at the high level, the transmission gate 172′ maintains theprevious off state, thereby preventing from transferring the stored rowaddress therethrough. When the clock φ_(R1) is then at the high level,the row address providing circuit 168 is isolated with the output of thelatch 164 by means of the gate 172. When the first bank row addressreset signal φ_(RAR1) then goes to a high level, NAND Gates 182 and 184output the row address data stored in the latch 178 and itscomplementary data therein, respectively. Consequently, a row addressRAI and its inverted row address {overscore (RAI)} from the circuit 172are fed to the row decoder in the first bank 12. It will be noted that,when φ_(R1) and φ_(R2) are both at high levels, the control signal RABPUbecomes high by means of the logic circuit 158, thereby disabling theinput buffer 70 in order to prevent the power consumption due to theactive or normal operations of all banks.

On the other hand, in the refresh operation such as a CBR or a selfrefresh operation, the refresh signal O_(RFH) is at a low level andφ_(RFH) is at a high level. In case of 2-bank refresh operation, andφ_(R1) and φ_(R2) are also at high levels, as will be discussed indetail hereinbelow in connection with FIG. 19. Signals φ_(RAR1) andφ_(RAR2) are also at high levels. Thus, the input buffer 70 and tristateinverter 160 are both in off states and at the same time, transmissiongates 172, 172′ and 194 are in off states while transmission gates 188and 188′ are in on states. Thus, a count address signal RCNTI from aknown address counter (not shown), which was stored into a latch 192 viathe transmission gate 194 turned on by φ_(RFH) being at a low levelprior to the refresh operation, are fed to the row decoder correspondingto each bank via transmission gates 188 and 188′, latches 178 and 178′and NAND gates 182, 184, 182′ and 184′. After that time, operations ofselecting word lines of each row decoder and then refreshing memorycells thereon are of the same manners as conventional DRAMs.

Addresses SRA10 and SRA11 for use in the multifunction {overscore (RAS)}buffer may use row addresses RA10 and RA11 from the row address buffer60. However, since the addresses RA10 and RA11 are generated with sometime delays, separated row address buffers which may operate in fasterspeed may be provided on the same chip for independently generating theaddresses SRA10 and SRA11.

4. Operation Mode Set Circuit

The synchronous DRAM of the present invention is designed so that systemdesigners choose desired ones of various operation modes in order toamplify the convenience of use and enlarge the range of applications.

FIG. 13 is a block diagram for the operation mode set circuit 58. A modeset control signal generator 200 generates a mode set signal φ_(MRS) inresponse to signals φ_(C), φ_(RP) and φ_(WRC) generated upon theissuance of the operation mode set command. An address code register202, in response to the power-on signal φ_(VCCH) from the power-oncircuit 203 and the mode set signal φ_(MRS), stores address codes MDST0to MDST6 depending on addresses from the row address buffer and producesthe codes MDST0 to MDST2 and MDST4 to MDST6 and a column addressing modesignal φ_(INTEL). A burst length logic circuit 204 produces a burstlength signal SZn generated with logic combination of the codes MDST0 toMDST2. Wherein n represents a burst length indicated as the number ofsystem clock cycles. A latency logic circuit 206 produces a {overscore(CAS)} latency signal CLj generated with logic combinations of the codesMDST4 to MDST6. Wherein j represents a {overscore (CAS)} latency (or{overscore (CAS)} latency value) indicated as the number of system clockcycles.

FIG. 14 is a diagram showing a schematic circuit diagram for the modeset control signal generator 200 and FIG. 20 is a timing diagramassociated with the operation mode set or program.

In the present embodiment, programming the operation modes isaccomplished by applying the operation mode set command and at the sametime, addresses A₀ to A₇ to address input pins according to thefollowing Table 1.

TABLE 1 Column {overscore (CAS)} latency j Addressing Way Burst Length nA6 A5 A4 j A3 Way A2 A1 A0 n 0 0 1 1 0 0 1 2 0 1 0 2 0 Binary 0 1 0 4 01 1 3 0 1 1 8 1 0 0 4 1 Interleave 1 1 1 512 The {overscore (CAS)}latency j related with a maximum system clock frequency is representedas the following Table 2.

TABLE 2 Maximum System Clock {overscore (CAS)} Latency j Frequency (MHZ)j 33 1 66 2 100 3

It will be noted that values of {overscore (CAS)} latency j in the aboveTables represent the number of system clock cycles and {overscore (CAS)}latency values related to maximum clock frequencies may be changedaccording to the operation speed of a synchronous DRAM.

For example, if a system designer want to design a memory system with abinary column addressing way and a continuous 8-word data access at 100MHZ, the minimum selection value of the {overscore (CAS)} latency j is3. If the {overscore (CAS)} latency value of 3 has been chosen,addresses A₀ to A₇ for setting the operation modes is 1, 1, 0, 0, 1, 1,0 and 0, respectively. It has been already discussed that selecting oneof both banks was address A₁₁. Remaining addresses thereof areirrelevant to logic levels.

After the selection of operation modes suitable for a data transfersystem and then the determination of addresses for setting the operationmodes, mode set programming of the synchronous DRAM is performed,applying the mode set command and the predetermined addresses tocorresponding pins of the chip. Referring to FIG. 20, the mode setcommand and the addresses ADD is applied thereto at a time t₁. Then,φ_(RF) from the {overscore (RAS)} buffer and signals φ_(C) and φ_(WRC)from a {overscore (CAS)} buffer and a {overscore (WE)} buffer as will bediscussed later go to high levels. In the mode set control signalgenerator 200 as shown in FIG. 14, the signals φ_(C), φ_(RP) and φ_(WRC)which are all high render a signal φ_(WCBR) to go low. When the rowaddress reset signal φ_(RARi) is then at a high level, the row addressbuffer of NAND gate 208 are all at high levels, thereby causing the modeset signal φ_(MRS) to go high.

FIGS. 15A-15C are diagrams showing circuit diagram for the address coderegister 202. The address code register 202 comprises first registerunits for storing second logic levels (low levels) upon the power-on andaddress signals RA₀, RA₂ to RA₄ and RA₆ in the mode set operation afterthe power-up in response to the node set signal φ_(MRS), and secondregister units for storing first logic levels (high levels) upon thepower-on and address signals RA₁ and RA₅ in the mode set operation afterthe power-up in response to the mode set signal φ_(MRS). Each of thefirst register units illustrated in FIG. 15A is comprised of a tristateinverter 210 including p-channel MOS transistors 212 and 214 andn-channel MOS transistors 216 and 218, a latch 222 connected to anoutput terminal of the inverter 210 and p-channel MOS transistor 220whose channel is connected between the power supply voltage Vcc and theoutput terminal and whose gate is coupled to the power-on signalφ_(VCCH). Since the power-on signal φ_(VCCH) is low until the supplyvoltage Vcc reaches minimum voltages to carry on internal normaloperation after the application thereof, i.e., on the power-on, eachfirst register unit makes corresponding address code MDSTI or theregister unit illustrated in FIG. 15B makes addressing mode signalφ_(INTEL) set at a low level on power-on by the conduction of p-channelMOS transistor 220. Each second register unit illustrated in FIG. 15Ccomprises a tristate inverter 210′ including p-channel MOS transistors212′ and 214′ and n-channel MOS transistors 216′ and 218′, an n-channelMOS transistor 219 whose channel is connected between an output terminalof the inverter 210′ and the reference potential (ground potential) andwhose gate is coupled to an inverted signal of φ_(VCCH), and a latch222′ connected to the output terminal of the inverter 210′. Each secondregister unit makes the address code MDST1 or MDST5 latched high uponthe power-on. However, in the mode set operation after the power-up,i.e., after the supply potential Vcc reaches at least the minimumoperating voltages, since φ_(VCCH) is high, inverters 210 and 210′ areturned on in response to the high level signal φ_(MRS) and latches 222and 222′ then store row addresses RAI from the row address buffer 60,thereby outputting address codes MDSTI having the same address values asthe row addresses RAI. Thus, if the mode set program is performed, eachaddress code of MDSTI is the same value as the corresponding address.MDST3 corresponding to the address signal RA₃ is the signal φ_(INTEL)which represents a way of column addressing. If A₃=0 (low level), thesignal φ_(INTEL) becomes low and a column address counter as discussedhereinbelow counts in a binary increasing manner. If A₃=1 (high level),the signal φ_(INTEL) becomes high representing an interleave mode.

FIG. 16 is a diagram showing a schematic circuit diagram for the latencylogic circuit 206 which selects to send to a high level only one oflatency signals CL1 to CL4 with the logic combination of address codesMDST4 to MDST6 associated with,the {overscore (CAS)} latency. Upon thepower-on, since MDST5 is high and MDST4 and MDST6 are low, only CL2becomes high.

FIG. 17 is a diagram showing a schematic circuit diagram for the burstlength logic circuit 204 for selecting one of signals SZ{overscore (2)}to SZ{overscore (512)}, each of which represents a burst length, withthe logic combination of address codes MDST0 to MDST2 associated withthe burst length. For example, if address codes MDST0 to MDST2 are allat high levels, only the signal SZ{overscore (512 )} of SZ{overscore(2)} to SZ{overscore (512)} is high and signals SZ4 to SZ512 are allhigh. Thus, as will be discussed hereinbelow, continuous 512-word (fullpage) outputs via data output buffer in response to the signals. Uponthe power-on, since MDST1 is high and MDST0 and MDST2 are low, only thesignals SZ4 and SZ{overscore (4)} are high.

Consequently, selected operation modes are determined by the storage ofcorresponding addresses to latches 222 and 222′ when the mode set signalφ_(MRS) is at the high level. After the address codes have been storedto corresponding latches 222 and 222′, an auto-charge operation isperformed according to one characteristic feature of the presentinvention. By performing a high speed precharge without any separateprecharge commands, precharging time is reduced and next operation suchas the active operation is also performed immediately without a standbystate.

FIG. 18 is a circuit diagram showing an auto-precharge control signalgenerator 223 for performing the auto-precharge upon the exit of selfrefresh or in the mode set program. The self refresh signal φ_(SELF) isat a high level in the self refresh operation and at a low level inremaining time excluding the self refresh operation. Thus, the output ofNAND gate 224 is at a high level in the mode set program. When φ_(RARi)reaches to a high level as seen in FIG. 20, the output of NOR gate 232goes to a high level. At this time, φ_(CLK) is at a low level. Whenφ_(CLK) then goes to a high level, the output of NAND gate 226 goes froma low level to a high level after a time delay determined by a delaycircuit 230. Consequently, the auto-precharge control signal generator223 produces an auto-precharge signal O_(AP) having a short low pulseafter O_(MRS) have gone high. Likewise, upon completion of the selfrefresh operation, O_(SELF) goes from high to low and the circuit 223then generates the auto-precharge signal O_(AP) having the short lowpulse. Returning to FIG. 9, the signal O_(AP) inputs to a NAND gate 152.Thus, the NAND gate 152 produces a short high pulse with the short lowpulse O_(AP), thereby turning on n-channel transistors 148 and 150. Thelatches 154 and 156 then store high levels, thereby causing φ_(SC1) andφ_(RC2) to go to low levels. Once either φ_(RC1) or φ_(RC2) goes to lowlevels, φ_(Ri) and φ_(RARi) goes to low levels in sequence and then theprecharge operation is performed.

On the other hand, if the synchronous DRAM of the present invention isused without the mode set programming, i.e., in a default mode,p-channel transistors 220 and n-channel transistors 219 as shown in FIG.15 are all turned on by the power-on signal φ_(VCCH) which is low uponthe power-on. Thus, latches 222 store low levels and latches 222′ storehigh levels. Address codes MDST0, MDST2, MDST4 and MDST6 and φ_(INTEL)then become low levels and the codes MDST1 and MDST5 also become highlevels. Consequently, in the default mode, {overscore (CAS)} latency of2, binary address mode and burst length of 4 are selected automatically.

5. Column Control Signal Generator

FIG. 19 is a diagram showing a schematic circuit diagram for a rowmaster clock generator 62 for generating the row master clock φ_(Ri) inresponse to the {overscore (RAS)} clock φ_(RCi) from the {overscore(RAS)} buffer 56. As shown in FIG. 19, if the i-th bank is activated,φ_(RCi) goes to a high level and the i-th bank row master clock φ_(Ri)then goes to a high level via NOR gate 234 and inverters. However, ifφ_(RCi) goes to a low level to precharge, φ_(Ri) goes to a low levelafter a different time delay according to each {overscore (CAS)}latency. That is, when the value of the {overscore (CAS)} latency j is1, i.e., CL1=high and CL2=CL3=low, φ_(Ri) goes to the low level after atime delay passing delay circuits 236, 238 and 240 mainly. When thevalue the {overscore (CAS)} latency j was set to 2, φ_(Ri) goes to thelow level after a time delay passing delay circuits 238 and 240 mainly.When the value of the {overscore (CAS)} latency j was programmed to 3,φ_(Ri) goes to the low level after a time delay passing the delaycircuit 240 mainly. Thus, the higher the frequency of system clock CLK,the shorter the time delay causing φ_(Ri) to go low. Such time delaysallow column selection signals to have a sufficient time margin beforethe beginning of precharge cycle in a write operation, thus correctlywriting data into cells and also ensuring that continuous 2-bit dataoutputs via output pin after precharge command in a read operation. Inthe present embodiment, the time delay in case of J=1 is about 19 ns andthe time delays in case of j=2 and j=3 are respectively about 6 ns and 3ns.

The row control clock generator 62 as shown in FIG. 3 is a conventionallogic circuit for generating clocks showing in the timing diagram ofFIG. 10. The row address reset signal φ_(RARi) rises to a high levelafter the rising edge of φ_(Ri) and falls to a low level after thefalling edge of φ_(X). The word line driving signal φ_(X) rises to ahigh level after the rising edge of φ_(RARi) and falls to a low levelafter the falling edge of φ_(Ri). The signal φ_(S) generated by thesignal φ_(X) activates sense amplifiers selected with the blockinformation signal BLS which is produced by decoding row addresses.Signal φ_(RALi) for enabling the column decoder goes to a high levelafter the rising edge of φ_(RARi) and goes to a low level after thefalling edge of φ_(RCi). Signal φ_(RCDi) for guaranteeing t_(RCD) goesto a high level after the rising edge of φ_(S) and goes to a low levelafter the falling edge of φ_(Ri).

FIG. 21 is a schematic circuit diagram showing a logic circuit forgenerating signals φ_(YEi) and φ_(RECi) which enable {overscore (CAS)}chain circuits. The signal φ_(YECi) is a delayed signal of φ_(RCDi).Column enable signal φ_(YEi) is a signal having a timing as shown inFIG. 10 by gating of φ_(RCDi) and φ_(Ri).

FIG. 11 is a schematic circuit diagram showing the high frequency clockgenerator according to the present invention which serves to multiplythe frequency of the internal system clock upon the occurrence ofprecharge command where a low frequency external system clock such as anexternal system clock CLK of 33 MHZ or less in the present embodiment isused. The high frequency clock generator 68 comprises a circuit means242 for generating a pulse depending on the precharge command, a gate248 for logically summing the generated pulse with the internal systemclock φ_(CLK) to generate a multiplied system clock and a transmissiongate 252 for transferring the multiplied system clock in response to apredetermined latency.

Referring to FIG. 22 showing a timing diagram for read and prechargeoperations at a system clock CLK of 33 MHZ and a burst length of SZ4,precharge command for read-out bank is issued at time t₄. φ_(RCi) thengoes from a high level to a low level and the output terminal A of thepulse generator 242 thereby outputs the pulse having a pulse widthdepending on a given time delay of a delay circuit 244 or 244′. Thispulse is summed with the internal system clock φ_(CLK) by means of gates246 to 248, thereby resulting in outputting a multiplied system clockvia NAND gate 248. NOR gate 254 outputs a high level since CL1 is highand φ_(EWDC) is high only in a write operation. Thus, the output of thegate 248 outputs via turned-on transmission gate 252. At this time, atransmission gate 250 is off. Thus, since internal circuits operate withan internal system clock CNTCLK9 having the multiplied operationfrequency after the precharge command, data output can be accomplishedat a high speed and the precharge operation can be completed within ashorter time period after the precharge command. When the system clockCLK is above 33 MHZ, CL1 is at a low level. Thus, NOR gate 254 outputs alow level and the transmission gate 252 is off. Thus, the transmissiongate 250 is turned off and CNTCLK9 is equal to the clock φ_(CLK).

Data Paths

Data paths mean paths for outputting the developed data on bit lines viadata output buffers in a read operation and feeding data being inputtingvia data input buffer to bit lines in a write operation. FIG. 23 showscircuit blocks associated with the data paths. For purposes ofsimplicity, it will be noted that the drawing shows circuit blocks ondata paths associated with two sub-arrays.

Referring to FIG. 23, an I/O line selection and precharge circuit 38 isconnected to the first I/O bus 26R associated with one of sub-arrays inone of memory cell arrays 20TL, 20BL, 20TR and 20BR and to the secondI/O bus 26L associated with another sub-array therein as discussed alongwith FIG. 1. The circuit 38 receives the block information signal BLSfor designating a sub-array including a word line selected by the rowdecoder 18 and in response to this information signal, serves to couplean I/O bus associated with the sub-array to PIO bus 256. Also, in areading operation, since data presents on two pairs of four pairs of I/Olines in a selected I/O bus, the circuit 38 precharges remaining twopairs of the four pairs and PIO line pairs corresponding thereto.

FIG. 24 is a diagram showing a schematic circuit diagram for the I/Oprecharge and selection circuit 38. When the block information signalBLS from the row decoder 18 is at a low level, transfer switches 258 and258′ are all in off states and precharge circuits 260 are all turned on,thereby precharging I/O line pairs I/O₀, {overscore (I/O₀)} to I/O₃{overscore (I/O₃)} to VBL $\left( {= {\frac{1}{2}{Vcc}}} \right).$

When the block information signal BLS is at a high level to transferdata, the switches 258 and 258′ are in on states while the prechargecircuits 260 are in off states. Now assume that I/O line pairs being totransfer data is the second I/O line pairs I/O₂, {overscore (I/O₂)} andI/O₃, {overscore (I/O₃)}. Then, an I/O line precharge signal IOPR1 goesto a low level and its complement signal {overscore (IOPR1)} goes to ahigh level. Thus, precharge circuits 262 and equalizing circuits 264 areturned on and the I/O line pairs I/O₀, {overscore (I/O₀)} and I/O₁,{overscore (I/O₁)} are then subsequently precharged and equalized to onethreshold voltage below the supply voltage (Vcc−V_(t)). Wherein V_(t) isa threshold voltage of n-channel MOS transistor. However, since theprecharge circuits 262′ and equalizing circuits 264′ associated with theI/O line pairs transferring data are all in off states, the data thereonis transferred to corresponding second PIO line pairs PIO₂, {overscore(PIO₂)} and PIO₃, {overscore (PIO₃)} via transfer switches 258′ in thereading operation. In the same manner, data on PIO line pairs cantransferred to corresponding I/O line pairs in write operations.

Returning to FIG. 23, an I/O sense amplifier 266 is activated to amplifydata on the PIO bus 256 with a control signal φ_(IOSE) which isgenerated in response to the block information signal in a readoperation. The I/O sense amplifier 266 is a know circuit which may befurther including a latch for storing data at its output terminal.

The output of the I/O sense amplifier 266 is coupled to the data outputmultiplexer via the data bus DBI. It will be noted that the data bus DBIis one of data buses DB0 to DB7, as shown in FIG. 1. Data line pairsDIO₀, {overscore (DIO₀)} to DIO₃, {overscore (DIO₃)} constituting thedata bus DBI are correspondingly connected to PIO line pairs PIO₀,{overscore (PIO₀)} to PIO₃, {overscore (PIO₃)} constituting the PIO bus256 via the sense amplifier 266.

FIG. 25 is a diagram showing a schematic circuit diagram for the dataoutput multiplexer 268 which are comprised of precharge circuits 263aand 263 d, latches 270, tristate buffers 272, first latches 274 a to274 d, isolation switches 276, second latches 278 a to 278 d and datatransfer switches 280, all of which are connected in series between therespective data line pairs and a common data line pair CDL and{overscore (CDL)}. In the same manner as previously discussed aboutprecharging of I/O line pairs I/O₀, {overscore (I/O₀)} to I/O₃,{overscore (I/O₃)}, the precharge circuits 263 a to 263 d respond to aDIO line precharge signal DIOPR1 and its complement {overscore (DIOPR1)}in a read operation, thereby causing two data line pairs transferringdata to be prevented from precharging and the remaining data line pairsto be precharged. Latches 270 are respectively connected to the datalines DIO₃, {overscore (DIO₀)} to DIO₃, {overscore (DIO₃)} for storingdata thereon. Tristate buffers 272 are respectively connected betweenthe data lines DIO₀, {overscore (DIO₀)} to DIO₃, {overscore (DIO₃)} andfirst latches 274 a to 274 d for outputting inverted data thereon.However, tristate buffers connected with data lines being precharged areturned off. First latches 274 a-274 d are respectively connected tooutput terminals of the tristate buffers 272 for storing datatransferred via the data lines and the tristate buffers. Each of secondlatches 278 a to 278 d is connected in series with corresponding firstlatch via corresponding isolation switch. The second latches 278 a-278 dare connected to a pair of common data lines {overscore (CDL)} and CDLvia corresponding data transfer switches 280. The data transfer switches280 are sequentially turned on in response to data transfer signalsRDTP0 to RDTP3 which are high level pulses generated in sequence bycolumn address signals, thereby sequentially outputting data stored inthe second latches to the common data lines {overscore (CDL)} and CDLvia the first latches. Thus, as will be discussed in more detailhereinafter, data stored in serial registers 274 and 278 which arecomprised of the first and the second latches 274 a to 274 d and 278 ato 278 d outputs in sequence on the common data lines {overscore (CDL)}and CDL in response to the data transfer signals RDTP0 to RDTP3. Inprecharge operations of the data line pairs DIO₃, {overscore (DIO₀)} toDIO₃, {overscore (DIO₃)}, since the tristate buffers 272 are held in offstates, there is no destruction of data stored in the first and secondregisters 274 and 278. However, where data stored in the second register278 waits a long time before transmission via transfer switches 280,i.e., in case of a long latency, if new data is transferred from dataline pairs, the previous data stored in the second register 278 will bedestroyed. Also, in case of use of a low frequency system clock, sincethe data transfer signals RDTP0 to RDTP3 are generated in synchronismwith the system clock, such destruction of data may be occurred. Suchdata destruction due to data contention may substantially occur in a{overscore (CAS)} interrupt read operation, i.e., such operation thatbefore the completion of burst operation during a sequential data readoperation based on the established burst length, an interrupt request isissued and a next sequential data read operation of the burst length isthen carried out with no break or no wait, depending on the columnaddress signals. Thus, to prevent an erred operation due to such datacollection, the isolation switches 276 are connected between the firstand the second latches. A control signal φ_(CL) for controlling theisolation switches is a high level pulse signal upon the {overscore(CAS)} interrupt request in case of long {overscore (CAS)} latencyvalues of 3 and 4. The data lines {overscore (CDL)} and CDL areconnected to a known data output latch 282.

Returning to FIG. 23, the data output buffer 284 is connected with dataoutput lines DO and {overscore (DO)} from the data output multiplexer268, serving to feed to an input/output pad (not shown) a sequentialdata synchronous to the system clock which is defined in dependence upona burst length in a read operation. There is a circuit diagram for thedata output buffer 284 in FIG. 26. In the drawing, transfer switches 286and 286′ respectively transfer data on the lines DO and {overscore (DO)}to lines 288 and 290 in synchronism with a system clock φ_(CLK) of agiven frequency (a frequency above 33 MHZ in the present embodiment),but in a synchronism with a system clock φ_(CLK) of the given frequencyor below the given frequency. As will be explained hereinafter, acontrol signal φ_(YEP) is held high at a system clock of 33 MHZ or below33 MHZ, i.e., at a {overscore (CAS)} latency value of 1 and held low ata system clock of a frequency above 33 MH. Latches 92 are respectivelyconnected to the lines 288 and 290 for storing data thereinto. A gatecircuit 310 comprised of NAND gates 294 to 298 and transistors 300 and302 is connected between the lines 288 and 290 and driving transistors304 and 306. The source of a p-channel MOS transistor 300 is coupled toa boosted Voltage Vpp from a known boost circuit for driving thetransistor 304 without loss of its threshold. The gate circuit 310serves to inhibit the output of data on the data input/out line 308 inresponse to a control signal φ_(TRST) which goes to a low level uponeither completion of a burst read operation or occurrence of a dataoutput masking operation.

Returning again to FIG. 23, the data input buffer 312 is connectedbetween a data line DI and the line 308 for converting external inputdata on the line 308 into CMOS level data and producing internal inputdata synchronous with the system clock φ_(CLK). The data input buffer312 may be comprised of previously mentioned input buffer for beingenabled by a signal φ_(EWDC) which is at a high level in a writeoperation, and converting an external input data into a CMOS level data;and previously mentioned synchronization circuit for receiving theconverted input data from the input buffer and then producing aninternal input data synchronous with the system clock φ_(CLK). Thus,whenever the clock φ_(CLK) goes to a high level in a write operation,the data input buffer 312 may be a buffer circuit for sequentiallysampling a serially inputting data and then outputting a resultingserial data on the data line DI.

A data input demultiplexer 314 serves to sample the serial data on theoutput line DI of the data input buffer 312 with write data transfersignals being sequentially generated in synchronism with the systemclock, thereby grouping into parallel data of predetermined bits (2-bitparallel data in the present embodiment) and supplying the groupingparallel data to corresponding data line pairs.

FIG. 27 is a diagram showing a schematic circuit diagram for the datainput demultiplexer 314. The demultiplexer 314 comprises selectionswitches 316 a to 316 d connected to the data line DI for sampling totransform the serial data on the data line DI into the parallel data inresponse to write data transfer signals WDTP0 to WDTP3. Each of latches320 a to 320 d are connected to the corresponding selection switch forstoring the sampled data. The outputs of the latches 320 a to 320 d arerespectively connected to the data lines DIO₀, {overscore (DIO₀)}, toDIO₃, {overscore (DIO₃)} via switches 322 a to 322 d, each of which is aNAND gate enabled in a write operation, and buffers 324 a to 324 d. Thesignal φ_(WR) gating NAND gates 322 a to 322 d is a signal being at ahigh level in a write operation. Each of the buffers 324 a and 324 d isa tristate inverter which is composed of a p-channel and an n-channeltransistors 326 and 328. P-channel transistors 318 a to 318 drespectively connected between the selection switches 316 a and 316 dand the latches 320 a and 320 d allow to, in response to the controlsignal WCA1 and its complement {overscore (WCA1)}, transfer a 2-bitparallel data, alternating two groups of first data line pairs DIO₀,{overscore (DIO₀)}, and DIO₁, {overscore (DIO₁)} and DIO₃, {overscore(DIO₃)}, and at the same time, precharge in such a manner as prechargingone group thereof while the other group thereof is transferring theparallel data. That is, when the control signal WCA1 is at a high levelin a write operation, transistors 318 c and 318 d are in off states.Thus, data stored in latches 320 c and 320 d in response to the signalsWDTP2 and WDTP3 is transferred to the second data line pairs DIO₂,{overscore (DIO₂)} and DIO₃, {overscore (DIO₃)} via switches 322 c and322 d and buffers 324 c and 324 d. At this time, since {overscore(WCA1)} is low, transistors 318 a and 318 b are in on states, andbuffers 324 a and 324 b are thereby in off states. Thus, the first dataline pairs DIO₀, {overscore (DIO₀)} and DIO₁, {overscore (DIO₁)} areprecharged to the supply potential Vcc by precharge circuits 263 a and263 b shown in FIG. 25. When WCA1 then goes to a low level, thetransistors 318 c and 318 d goes to on states and the tristate buffers324 c and 324 d then become off. Thus, likewise, the second data linepairs are precharged and the first data line pairs transfer a 2-bitparallel data.

Returning to FIG. 23, data transferred via the bidirectional data busDBI from the data input demultiplexer 314 is transferred to PIO linepairs 256 via the PIO line driver 330.

FIG. 28 is a drawing showing a schematic circuit diagram for the PIOline driver 330 which comprises switches 332 responsive to a bankselection signal DTCPi and the block selection signal BLS for passingdata on the data line pairs DIO₀, {overscore (DIO₀)} to DIO₃, {overscore(DIO₃)}, buffers 334 connected between the switches 332 and the PIO linepairs PIO₀, {overscore (PIO₀)} to PIO₃, {overscore (PIO₃)} foramplifying data inputting via the switches 332 to supply tocorresponding PIO line pairs, and precharge and equalizing circuits 336each connected between two lines constructing each PIO line pair forprecharging and equalizing the PIO line. It should be noted that thebuffers 334 and the precharge and equalizing circuits 336 are the sameconstructions as the buffers 324 a to 324 d in FIG. 27 and the prechargeand equalizing circuits 260, 262, 262′, 264 and 264′ in FIG. 24, andtheir operations are also associated with each other in a writeoperation. The PIO line driver 330 isolates between the data bus DBI andthe PIO line pairs 256 with the signal DTCPi being at a low level in aread operation. However, in a write operation, data on the PIO linepairs 256, which is transferred from the data bus DBI by means of thedriver 330, is transferred to corresponding I/O line pairs selected bythe I/O precharge and selection circuit 38. Since the data transmissionis alternately accomplished every two pairs, if first I/O line pairsI/O₀, {overscore (I/O₀)} and I/O₁, {overscore (I/O₁)} of the left sideI/O bus 26R, which are correspondingly connected with the first PIO linepairs PIO₀, {overscore (PIO₀)} and PIO₁, {overscore (PIO₁)}, aretransferring data thereon, second PIO line pairs PI₂, {overscore (PIO₂)}and PIO₃, {overscore (PIO₃)} and second I/O line pairs I/O₂, {overscore(I/O₂)} and I/O₃, {overscore (I/O₃)} of the left I/O bus 26R will beprecharging.

Column Control Circuit

Column control circuit is a circuit for generating control signals tocontrol circuits related to the data paths.

FIG. 4 is a schematic block diagram showing the column control circuitaccording to the present invention. In the drawing, a {overscore (CAS)}buffer 338 receives the external column address strobe signal {overscore(CAS)} and the internal system clock φ_(CLK) and then generates pulsesignals φ_(C), φ_(CA), BITSET and φ_(CP).

A {overscore (WE)} buffer 340 receives the external write enable signal{overscore (WE)}, the system clock φ_(CLK), the pulse signals φ_(C) andφ_(CA) from the {overscore (CAS)} buffer 338 and various control signalsfor generating write control signals φ_(WR), φ_(EWDC) and φ_(WRC) in awrite operation.

A DQM buffer 342 receives external signal DQM and the internal systemclock φ_(CLK), and then generates a data input/output masking signalO_(DQM) to inhibit the input and the output of data.

A column address buffer 344 receives external column addresses A₀ to A₉in synchronism with the system clock φ_(CLK), thereby latching thecolumn addresses in response to the pulse signal φ_(CA) from the{overscore (CAS)} buffer 338, and then producing column address signalsECA0 to ECA9.

A column address generator 346 is a counter circuit which is composed ofa predetermined number of stages or bits (nine bits in the presentembodiment). The counter may carry out counting operation either in asequential or binary address mode or in an interleave address modeaccording to the column addressing mode signal φ_(INTEL). Stages of thecounter latch the column address signals from the column address buffer344 in response to the pulse BITSET, and lower stages thereof associatedwith the burst A length signal SZn perform the counting operation withthe clock CNTCLK9, starting from the column address signals latchedtherein, and then produce successive column address signals according toa selected address mode. However, remaining stages produce initialcolumn address signals latched therein. A column address reset signalφ_(CAR) is a signal for resetting the counter at the end of the burstlength, i.e., after completion of a valid data output.

A burst length counter 350 is a conventional 9-stage (or 9-bit) binarycounter counting pulses of the clock φ_(CLK) after being reset by thepulse signal BITSET from the {overscore (CAS)} buffer. The counter 350may also be reset by the column address reset signal φ_(CAR). Since theBITSET signal is a pulse generated upon activation of {overscore (CAS)},the counter 350 is re-count the number of pulses of the clock φ_(CLK)after the activation of {overscore (CAS)}. However, the signal φ_(CAR)is a signal stopping the counting operation of the counter 350. Thus, ina {overscore (CAS)} interrupt operation, the activation of {overscore(CAS)} during the output of valid data renders the counting operation ofthe counter to restart.

A burst length detector 352 receives the counting value from the counter350 and the burst length signal SZ{overscore (n)} from previouslymentioned mode set circuit 58, and then generates a signal COSRindicating of the end of the burst.

A column address reset signal generator 354 serves to generate thesignal φ_(CAR) resetting the column address generator 346 in response tothe burst end signal COSR.

A data transfer control counter 348 is a counter which receives addresssignals CA0, CA1, FCA0 and FCA1 and then generates column addresssignals RCA0 and RCA1 synchronous to the system clock φ_(CLK). The clockCNTCLK9 is a clock artificially generated to shorten the precharge timewhen the system clock CLK of 33 MHZ or less is employed as previouslydiscussed. Thus, in this case, the column address signals CA0 and CA1 isnot signals synchronized with the system clock φ_(CLK). Thus, thecounter 348 exists in consideration of the reduction of the prechargetime at the system clock of 33 MHZ or less. If unnecessary, the columnaddress generator 346 receives φ_(CLK) in place of CNTCLK9, and a readand a write data transfer clock generators 356 and 358 may receive thecolumn address signals CA0 and CA1 instead of the outputs of the counter348, i.e., RCA0 and RCA1.

The read data transfer clock generator 356 receives the column addresssignals RCA0 and RCA1 synchronized with the system clock φ_(CLK) andthen generates read data transfer pulses RDTPm to output a serial datafrom the data output multiplexer 268 in a read operation.

The write data transfer clock generator 358 receives the signals RCA0and RCA1 and then generates write data transfer pulses WDTPm to output atime multiplexed parallel data from the data input demultiplexer 314 ina write operation.

The write data transfer clock generator 358 receives the signals RCA0and RCA1 and then generates write data transfer pulses WDTPm to output atime multiplexed parallel data from the data input demultiplexer 314 ina write operation.

1. {overscore (CAS)}, {overscore (WE)} and DQM Buffers

FIG. 29 is a drawing showing a schematic circuit diagram for the{overscore (CAS)} buffer 338, and FIG. 33 is a drawing showing a timingdiagram of a write operation employing system clock of 66 MHZ, burstlength of 4 and {overscore (CAS)} latency of 2.

In FIG. 29, an input buffer 70 is a circuit which is disabled in refreshand clock masking operations and converts input signals into internalCMOS level signals in read and write operations. A synchronizationcircuit 108 is connected to the input buffer 70 to synchronize the CMOSlevel {overscore (CAS)} signal from the input buffer with the systemclock φ_(CLK). A pulse generator 360 is connected to the synchronizationcircuit 108 to generated control pulses φ_(CA), φ_(CP) and BITSET.Referring to FIGS. 33A-33C comprised of FIGS. 33A and 33B the pulsesφ_(C), φ_(CA), φ_(CP) and BITSET are generated by the {overscore (CAS)}pulse being at a low level at time t₃. The high level pulse width ofφ_(C) is about one cycle of the system clock CLK, and the pulse width ofφ_(CA) is about one half cycle of the clock CLK while the pulse widthsof φ_(CP) and BITSET are about 5 to 6 nsec.

FIG. 30 is a drawing showing a schematic circuit diagram for the{overscore (WE)} buffer 340. In the drawing, an input buffer 70 is acircuit for converting the external write enable signal {overscore (WE)}into and internal CMOS level signal. A synchronization circuit 108stores the level shift signal from the input buffer 70 into a latch 362in synchronism with the system clock φ_(CLK). The input of a latch 366is coupled to the output of the latch 362 via a transfer switch 364turned on by the activation of {overscore (CAS)} for storing a highlevel thereinto in a write operation. A gate circuit 368 comprised ofgates is connected to the output of the latch 366. A shift register 370is connected to the gate circuit 368 for delaying one cycle of CLK aftera write command. A pulse generator 378 generates a short high levelpulse φ_(WRP) in a precharge cycle for resetting the shift register 370and the latch 366. Referring to FIGS. 33A-33C, when φ_(CA) is at a highlevel after issuance of a write command at time t₃, the latch 366 storesa high level. Since φ_(C) and at least one of φ_(RCD1) and φ_(RCD2) arealso at high levels at that time as discussed hereinabove, a NAND gate372 outputs a low level, thereby forcing a control signal φ_(EWDC) to gohigh. The low level output of the NAND gate 372 inputs to the shiftregister 370, thereby outputting low level therefrom after a delay ofone cycle of φ_(CLK). Then, a NAND gate 374 outputs a high level,thereby causing the control signal φ_(WR) to go high. Generating thecontrol signal φWR after a delay of one cycle of CLK is to accept anexternal input data at a next cycle of CLK after a write command. Thus,to accept an external input data at a write command cycle, it will beobvious to those skilled in the art that the shift register 370 may beomitted therefrom.

FIG. 31 is a drawing showing a schematic circuit diagram for the DQMbuffer 342, and FIG. 32 is a drawing showing an operation timing diagramfor the DQM buffer. Referring to FIG. 31, an input buffer 70 is a bufferfor converting an external signal DQM into a CMOS level signal. A shiftregister 382 is connected to the input buffer 70 for generating a dataoutput masking signal O_(DQM) in synchronism with the system clockφ_(CLK). Referring to FIG. 32, a data output masking command is issuedat time t₁. At this time, a latch 384 stores a low level. When φ_(CLK)387 is then at a high level, a latch 385 stores a high level. Whenφ_(CLK) 387 is then at a low level, a latch 386 stores a high level.When φ_(CLK) 388 is then at a high level, the signal O_(DQM) goes to alow level. Likewise, the signal O_(DQM) goes to a high level whenφ_(CLK) 389 is at a high level. Thus, inhibiting data output from thedata output buffer with O_(DQM) signal being at the low level isaccomplished by responding to the rising edge of the second clock ofφ_(CLK) after the issuance of the data output masking command. It willbe obvious to those skilled in the art that the time adjustment ofinhibiting data output therefrom may be accomplished by changing thenumber of shift stages.

2. Column Address Generator

The column address generator comprised of a column address buffer 344and a column address counter 346.

FIG. 34 is a drawing showing a schematic circuit diagram for the columnaddress buffer 344. The synchronous DRAM of the present embodiment usesten column address buffers which receive external column addressee A₀ toA₉, respectively. In the drawing, an input buffer 70 is a buffer forconverting the external column address signal A₁ into a CMOS leveladdress signal. The input buffer 70 is enabled by the signal φ_(RAL) andits output is coupled to a latch 392 via a transfer switch 390. Beforeφ_(CA) goes to a high level, the latch 392 stores an input columnaddress signal ECAI and then produces a column address signal FCAI viainverters. Only signals FCA0 and FCA1 are fed to the data transfercontrol counter 348. When φ_(CA) is at the high level due to theactivation of {overscore (CAS)}, a transfer switch 394 is turned on,thereby storing complement of the column address signal ECAI into alatch 398. The output of the latch 398 is coupled to switch meanscomprised of NAND gates 400 and 402 which is enabled by φ_(CAR). Theenabled NAND gates 400 and 402 provide column address signal CAI and itscomplement {overscore (CAI)}, respectively. The column address signalsCAI are fed and loaded to the column address counter 346, therebygenerating successive column address signals PCAI therefrom withcounting operation starting from the loaded column address signal. Thesignals PCAI output as column address signals CAI and {overscore (CAI)}via transfer switches 396, latches 398 and switches 400 and 402. Thus,transfer switches 394 and 396, latch 398 and switch 400 and 402constitute means for providing a starting column address with φ_(CA)pulse generated by the activation of {overscore (CAS)}, and providingsuccessive column address signals being counted from the starting columnaddress when the pulse φ_(CA) is at a low level. Thus, after theactivation of {overscore (CAS)} the successive column addresses, i.e.,serial steam of the external input column address and the internallygenerated column addresses can be generated at a high speed. It shouldbe noted that in the present embodiment, column address buffersassociated with column address signals CA0 and CA9 do not receivesignals PCA0 and PCA9. The signals CA9 has no relationship with thecolumn decoder because of using as a bank selection signal in case ofexecuting a {overscore (CAS)} interrupt operation. Signals CA0 and CA1are also signals for generating read data transfer clocks RDTPm andwrite data transfer clocks WDTPm which are respectively used in the dataoutput multiplexer 268 and the data output demultiplexer 314. SignalsCA1 to CA8 are utilized for column decoding.

FIG. 35 is a drawing showing a schematic block diagram for the columnaddress counter 346, and FIG. 36 is a drawing showing a schematiccircuit diagram for each stage in the column address counter. Referringto the drawings, the column address counter 346 is a 9-bit countercomprised of nine stages ST1 to ST9, and comprises a first counterportion including lower stages ST1 to ST3 and AND gates 404 and a secondcounter portion including upper stages ST4 to ST9 and AND gates 406. Thefirst counter portion may carry out counting operation in one of binaryand interleave modes, and the second counter portion may performcounting operation in the binary mode. In the first counter portion,i.e., 3-bit counter, selection of either the binary or the interleavemode is enforced by the logic level of the address mode signalφ_(INTEL). In the least significant stage ST1, an input terminal of acarry input signal CARI and a burst length input terminal SZ areconnected to the supply potential Vcc. Carry output signal CARO of thefirst stage ST1 inputs to a carry input signal CARI of the second stageST2, and AND gate 404 corresponding to the second stage ST2 ANDs thecarry outputs of the first and second stages ST1 and ST2. AND gate 404corresponding to the third stage ST3 ANDs a carry output of the thirdstage ST3 and the output of the AND gate corresponding to the secondstage ST2 which is connected to a carry input of the third stage ST3.The output of the AND gate associated with the most significant stageST3 of the first counter portion is connected to a carry input signalCARI of the least significant stage ST4 of the second counter portion. Acarry input signal CARI of each stage in the second counter portion iscoupled to the output of the AND gate of the previous stage. Each ANDgate 406 of the second counter portion inputs the output of the AND gateof previous stage and the output of the corresponding stage.

The column address counter 346 of the present invention may selectivelyperform one of both the binary and the interleave modes as an addresssequence in order to enhance a design flexibility for memory systemdesigners. The binary addressing mode is a mode representative ofgenerating successive addresses increasing by one from a given startingaddress, and the interleave addressing mode is a mode representative ofgenerating successive addresses in a specific way. The following Table 3represents the address sequence representative of the decimal number incase of the burst length of 8.

TABLE 3 Address Sequence (Burst Length n = 8) Binary Mode InterleaveMode 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 1,0,2,3,5,4,7,62,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,44,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,26,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1

FIG. 36A is a drawing showing a schematic circuit diagram for each stageof the first counter portion. Referring to the drawing, each stage ofthe first counter portion includes a carry portion 408 for generating acarry and a bit portion 410 for providing a bit output. The carryportion 408 comprises two latches 412 and 416, a transfer switch 414connected between the latches 412 and 416, an inverter 418 and atransfer switch 411 connected in series between an output terminal ofthe latch 416 and an input terminal of the latch 412. Likewise, the bitportion 410 also comprises latches 412′ and 416′, transfer switches 411′and 414′ are connected to a line 419 and a line 415 via an inverter 413.Input terminals of latches 412 and 412′ are connected to lines 422 and424, respectively. An initialization circuit 420 is connected betweenthe lines 422 and 424 for providing an initial condition, i.e., a lowlevel upon power-on to the latches 412 and 412′. The line 419 isconnected to an output terminal of a NOR gate 426, three input terminalsof which are respectively coupled to the clock CNTCLK9, the output of aNAND gate 428 and the signal BITSET. The NAND gate 428 receives theburst length signal SZn, a signal φ_(CARC) and the carry signal CARIwhich is the previous carry output signal CARO. Transfer switches 430and 432 are turned on in response to the signal BITSET and therebytransfers an initial carry value and an initial column address value (oran initial bit value) on lines 422 and 424, respectively. The modecontrol signal φ_(INTEL) is at a high level in the interleave mode andat a low level in the binary mode, as discussed hereinabove. Thus, thetransfer switches 430 and 432 turned on in the interleave moderespectively transfer a low level and the initial bit value CAI, and theswitches 430 and 432 both transfer the initial bit value CAI in thebinary mode.

FIG. 37 is an operation timing diagram for the circuit diagram of FIG.36A. Referring to FIGS. 36A and 37, when any one of input signals SZn,φ_(CARC) and CARI of NAND gate 428 is at a low level, NOR gate 426inhibits the output of the clock CNTCLK9, maintaining a low level on theline 419. Thus, transfer switches 414 and 414′ are in on states whiletransfer switches 411 and 411′ are in off states. At this time, oncetransfer gates 430 and 432 are turned on with the pulse signal BITSET ata high level, the carry output signal CARO and the bit output signalPCAI are respectively an initial carry value of a low level and aninitial bit value in an interleave mode while the carry output signalCARO and the bit output signal PCAI are both initial bit values CAI in abinary mode. Then the low level signal BITSET turns off the transferswitches 430 and 432 and thereby causes the previously preset initialcarry and bit values to be maintain thereon. Thus, the signal BITSET isa signal for respectively presetting initial carry and bit values intothe carry portion 408 and the bit portion 410 according to the modecontrol signal φ_(INTEL).

On the other hand, after the establishment of the initial values withthe preset signal BITSET, when the signals SZn, φ_(CARC) and CARI areall at high levels, the NOR gate 426 outputs the clock CNTCLK9. Then,the carry portion 408 and the bit portion 410 respectively output binarysequential count values starting from the preset initial values everycycles of the clock CNTCLK9. During such a sequential operation, if alow level carry signal CARI inputs to the NAND gate 428, the line 419becomes a low level, thereby freezing operations of the carry portion408 and the bit portion 410. That is, since transfer switches 411 and411′ are turned off, CARO and PCAI are respectively frozen to invertedones of binary values stored in latches 412 and 412′. When the signalCARI then goes to a high level, sequential operations are re-startedbeginning from the frozen values.

FIG. 36B is a diagram showing a schematic circuit diagram for each stageconstituting the second counter portion of FIG. 35. Constructions ofthis stage are identical to those excluding the carry portion 408 andthe mode control circuit 434 in the stage of FIG. 36A. Its operation isalso identical to that of the bit portion 410 of FIG. 36A. Thus,detailed explanation for each of the stages ST4 to ST9 will be omitted.

Returning to FIG. 35, it is assumed that the burst length of n has beenset by the operation mode program. Then, since burst length signalsassociated with burst length of n or less are all at high levels, onlystages receiving high level burst length signals SZn are enabled. Forexample, if the burst length n is 512 (full pages), the column addresscounter operates as a 9-bit counter. If burst length of n=32 isprogrammed, five lower stages ST1 to ST5 perform sequential countingoperations, and output signals PCA5 to PCA8 of upper stages ST6 to ST9respectively maintain initial input bit values, i.e., input columnaddress signals CA5 to CA8. Thus, the first counter portion comprised ofthree lower stages ST1 to ST3 outputs sequential binary or interleaveaddress signals PCA0 to PCA2 according to the mode control signal g andthe counter comprised of stages ST4 and ST5 outputs sequential binaryaddress signals PCA3 and PCA4 starting from input column addresses CA3and CA4, receiving carries from the first counter portion.

3. Column Decoder

As discussed hereinabove, the column address buffers 344 output columnaddress signals CA1 to CA8 inputting to the column decoder for selectingcolumns.

FIG. 38 is a drawing showing a schematic block diagram for the columndecoder according to the present invention. In the drawing, predecoders436 to 442 receive column adds signals CA1 and CA2, CA3 and CA4, CA5 andCA6 and CA7 and CA8, respectively and also receive a row address signalsRA11 or a column address signal CA9. The row address signal RA11 is usedas a bank selection signals in case of performing either an interleaveoperation of the first and second banks or an independent operationbetween both banks such as performing read or write operation andprecharge operation of the second bank after performing read or writeoperation and precharge operation of the first bank. If RA11 is low, thefirst bank is selected, while if RA11 is high, the second bank isselected. On the other hand, CA9 is a bank selection signal in case ofperforming a {overscore (CAS)} interrupt operation. The first bank isselected when CA9 is low., while the second bank is selected when CA9 ishigh.

The first predecoder 436 decodes column address signals CA1 and CA2,thereby generating predecode signals DCA{overscore (1)} {overscore (2)}to DCA12 and also generating a signal DCA2 and its complementDCA{overscore (2)} which are faster than the signals DCA{overscore (1)}{overscore (2)} to DCA12. Neighboring signals of the predecode signalsoverlaps a predetermined portion of each end. The output signals of thefirst predecoder 436 are fed to main decoders 444. NOR gates 446respectively input combinations of signals choosing one of predecodesignals DCA{overscore (3)} {overscore (4)} to DCA34 from the predecoder440 and one of predecode signals DCA{overscore (7)} {overscore (8)} toDCA78 from the predecoder 442, and their outputs are respectivelycoupled to the main decoder 444 so as to produce column selectionsignals CSL0 to CSL255.

FIG. 39A is a drawing showing a schematic circuit diagram for the firstpredecoder 436. In the drawing, NAND gates 448 are enabled by the bankselection signal RA11 or CA9, decode column address signals CA1 and CA2and their complements {overscore (CA1)} and {overscore (CA2)}. Afteractivation {overscore (CAS)}, a short low level pulse φ_(CP) resets NANDgates 451 and 454, thereby causing the output signals DCA{overscore (1)}{overscore (2)} to DCA12 to become low. When φ_(CP) is then at a highlevel (at this time, φ_(YEi) is high), the NAND gates 451 and 454 areenabled. It is now assumed that CA1 and CA2 have been at low levels.Then, NAND gate 448 a outputs a low level, and NAND gate 456 a thenoutputs a high level. Thus, DCA{overscore (1)} {overscore (2)} goes fromthe low level to a high level, while DCA{overscore (1)} {overscore (2)},DCA1,{overscore (2)} and DCA12 remain the low levels. When CA1 then goesto a high level and CA2 maintains the low level, this results in causingDCA1{overscore (2)} to go high. However, the NAND gate 448 a outputs ahigh level, thereby causing DCA{overscore (1)} {overscore (2)} to go lowafter delays via delay circuits 450 a and 452 a, NAND gates 451 a, 456 aand 454 a and an inverter. Thus, DCA{overscore (1)} {overscore (2)} goesto the low level with the time delay determined by the delay elementsafter going to the high level. Consequently, overlapped portions occurend portions between successive predecoding signals. These overlappedportions guarantee an error free write time during a write operation.

FIG. 39B is a drawing showing a schematic circuit diagram for one ofsecond predecoders 438 to 442. It should be noted that each secondpredecoder is a low enable circuit in which a selected predecode signalgoes to a low level.

FIG. 40 is a drawing showing a schematic circuit diagram for first oneof main decoders 444. Referring to the drawing, predecode signalDCA{overscore (1)} {overscore (2)} to DCA12 are respectively coupled toinput terminals of inverters 458 a to 458 d which are partitioned into afirst inverter group of inverters 458 a and 458 b and a second invertergroup of inverters 458 c and 458 d. One terminal of each of inverters458 a and 458 b constituting the first group is connected in common witha drain of a first transistor 462, while one terminal of each ofinverters 458 c and 458 d constituting the second group is connected incommon with a drain of a second transistor 464. The other terminal ofeach of the inverters 458 a to 458 d is connected to the supplypotential Vcc. Output terminals of the inverters are respectivelyconnected to latches 406 a to 460 d. Sources of first and secondtransistors 462 and 464 are connected in common with a drain of a thirdor pull-down transistor 466 whose source is connected to a referencepotential Vss such as a ground potential and whose gate is connectedwith the output of NOR gate 446 inputting predecode signalsDCA{overscore (3)} {overscore (4)}, DCA{overscore (5)} {overscore (6)}and DCA{overscore (7)} {overscore (8)} from the second predecoders 438to 442. Gates of the first and the second transistors 462 and 464respectively received DCA{overscore (2)} and DCA2. The input signals aregenerated in order of predecode signals DCA2 and DCA{overscore (2)},predecode signals DCA{overscore (3)} {overscore (4)}, DCA{overscore (5)}{overscore (6)} and DCA{overscore (7)} {overscore (8)} and overlappedpredecode signals DCA{overscore (1)} {overscore (2)} to DCA12. Thus,after the transistor 462 or 464 and the pull-down transistor 466 havebeen turned on, the inverters 458 a to 458 d can be turned on. It is nowassumed that column address signals CA1 to CA8 have been low. Then, thetransistor 462 is turned on and the transistor 466 is then turned on.The inverter 458 a is then turned on by the high-going signalsDCA{overscore (1)} {overscore (2)} band thereby the column selectionsignal CSL0 goes to a high level. Where the column address signal CA1then changes into a high level, DCA{overscore (1)} {overscore (2)} goesto a high level, thereby causing the column selection signal CSL1 to gohigh. However, the column selection signal CSL0 becomes from the highlevel to a low level after a predetermined delay, as discussed above,due to the low-going signal DCA{overscore (1)} {overscore (2)}. In thesame manner as discussed above, column selection signals overlappingpredetermined ones of end portions in response to column address signalsCA1 to CA8 being sequentially changed. Referring to FIG. 33B, whereinitial external column addresses A₀ and A₁ to A₈ are respectively at ahigh level and low levels, illustration is made on a timing diagramshowing timing relations between column address signals CA to CA8,signals DCA{overscore (1)} {overscore (2)} a and DCA1{overscore (2)} andcolumn selection signals CSL0 and CSL1. It can be understood in thedrawing that time periods for selecting columns are sufficientlyguaranteed by overlapped portions.

FIG. 41 is a timing diagram showing a read operation at the system clockfrequency of 100 MHZ, the burst length of 4 and the {overscore (CAS)}latency of 3. It can be understood in the drawing that sufficientread-out time periods can be guaranteed by overlapped portions ofsignals DCA{overscore (1)} {overscore (2)}, DCA1{overscore (2)} and CSL1where A₀ and A₁ to A₈ are initially at a high level and low levels,respectively.

4. Data Bus Control Circuit

It is very important that unnecessary internal operations are precludedto eliminate power consumption after completion of the burst length,i.e., after output or input of valid data. Such a control circuitcomprises the burst length counter 350, the burst length detector 352and the column address reset signal generator 354 as shown in FIG. 4.

The burst length counter 350 stops its counting operation when thecolumn address reset signal φ_(CAR) is at a low level. The counter 350is reset by a short high level pulse BITSET, thereby re-starting itscounting operation. Thus, the burst length counter 350 is a conventional9-bit binary counter whose clock input terminal is connected to thesystem clock φ_(CLK) and whose reset terminal is connected to the outputof a OR gate inputting the signal BITSET and complement of φ_(CAR).Count values CNTI (I=0, 1, . . . 8) of the counter 350 input to thecounter 350 input to the burst length detector 362.

FIGS. 42 and 43 show a schematic circuit diagram for the burst lengthdetector. The burst length detector 352 includes a logic circuitreceiving the count values CNTI and burst length signals SZn forgenerating a signal COSI informing of the completion of burst lengthafter activation of {overscore (CAS)}. For example, referring to FIG.41, once the pulse BITSET goes from the high level to the low levelafter the activation of {overscore (CAS)}, the counter 350 counts clocksof φCLK, thereby producing count signals CNT0 and CNT1. Since SZ4=1(high) in case of the burst length of 4, the burst length detector 352produces the signals COSI having a pulse width of one cycle of φ_(CLK)when CNT0 and CNT1 are all at high levels. On the other hand, the pulseφ_(C) being at the high level after the activation of {overscore (CAS)}renders to be latched low the output of a flip-flop comprised of NORgates 468 and 470 as shown in FIG. 43, thereby causing the signal COSRto go low as shown in FIG. 41B. Once COSI then goes to a high level, twoinputs of a NAND gate 474 become high after delay of a shift register472 with the system clock φ_(CLK). Thus, the output of the NOR gate 468goes low. At this time, since φ_(C) is low, the output of the NOR gate470 goes to a high level, thereby causing COSR to go to a high level.Thus, it can be understood in FIG. 4b that the low level signal COSR isa signal indicating of the burst length, i.e., four pulses of the systemclock CLK after the activation of {overscore (CAS)}. A delay circuit 476for providing time delays depending on {overscore (CAS)} latency valuesreceives the signal COSR and then outputs a signal COSDQ. Thus, it canbe seen that the signal COSDQ is a signal indicating of a burst lengthconsidering a {overscore (CAS)} latency. Referring to FIG. 41B, sincethe {overscore (CAS)} latency is 3 (CL3 is a high level), a transferswitch 478 is turned on, thereby producing the signal COSDQ that thesignal COSR is delayed by two cycles of the clock φ_(CLK). It has beenalready discussed that the signal COSDQ being at a high level disablesthe data output buffer.

FIG. 44 is a drawing showing a schematic circuit diagram for the columnaddress generator 354. Referring to FIG. 41 or FIG. 33, the signalφ_(RALi) had become high prior to the activation or {overscore (CAS)}.Then, after the activation of {overscore (CAS)}, NAND gates 482 and 484output high levels in response to the high-going pulse φ_(C). Thus, aNAND gate 480 constituting a flip-flop is latched to a low level,thereby allowing φ_(CAR) to go high. Likewise, a NAND gate 486 outputs alow level in response to the signal COSR going to a low level when φ_(c)is high since one of φ_(YEC1) and φ_(YEC2) maintains a high level atthis time. Thus, φ_(CARC) goes to a high level. Then once COSR goes to ahigh level, φ_(CAR) and φ_(CARC) goes to low levels. However, in case ofusing a system clock of a lower frequency such as 66 MHZ or less,signals φ_(RALi) and φ_(YEI) or φ_(YE2) rather than the signal COSR gofirst to low levels, thereby causing the signal φ_(CAR) to go low. Thus,the burst length counter 350 and the column address counter 346 arereset by the low-going signal φ_(CAR), thereby preventing unnecessaryoperations thereof.

5. Data Transfer Clock Generator

A data transfer clock generator is a circuit for generating clock fortransferring data via the data output multiplexer and the input datademultiplexer. The data transfer clock generator includes the datatransfer control counter 348 and the read and write data transfer clockgenerators 356 and 358.

The column address generator 346 is using the multiplied system clockCNTCLK9 as synchronization clock to assure a faster precharge time incase of using a system clock of 33 MHZ or less, as previously discussed.In such a case, since data must be transferred in synchronism with thesystem clock CLK, the data transfer control counter 348 is essentiallyrequired. However, if such a technique is unnecessary, i.e., if suchlower frequency system clock is not used, some modifications arerequired. Such modifications can be accomplished by the followingexplanation. That is, the column address counter 346 as shown in FIG. 35uses the system clock φ_(CLK) in place of the clock CNTCLK9 as asynchronous count clock. Selection circuits 391 as shown in FIG. 34respectively receive the lower 2-bit outputs PCA0 and PCA1 to producecolumn address signals CA0 and CA1. The read and write data transferclock generators 356 and 358 directly input the signals CA0 and CA1instead of outputs RCA0 and RCA1 from the data transfer control counter348.

FIG. 45 is a drawing showing a schematic block diagram for the datatransfer control counter 348 which comprises a 2-bit counter 488 and 490and selection circuits 492 and 494. The 2-bit counter receives columnaddress signals CA0 and CA1 from the column address buffers 344 forgenerating internal sequential column address signals starting from thesignals CA0 and CA1 in synchronism with the system clock φ_(CLK). Theselection circuits 492 and 494 serve to generate serial column addressstream with column address signals FCA0 and FCA1 from the column addressbuffers 344 and the internal sequential column address signals from the2-bit counter. Stages 488 and 490 constituting the 2-bit counter arerespectively identical in constructions to stages shown in FIGS. 36A and36B. The difference therebetween is to use the system clock φ_(CLK)instead of the clock CNTCLK9. Each of the selection circuits 494 and 492has the same construction as the selection circuit 391 of FIG. 34. Theinput signals ECAI of the transfer switch 394 and the input signal PCAIare respectively replaced by FCAI and the output of the corresponding2-bit counter (wherein I is 0 or 1). The signal COSR is also fed tothird inputs of NAND gates 400 and 402. Using the signal COSR in theselection circuits 492 and 494 is preventing unnecessary internaloperation thereof upon completion of burst length. Operation explanationfor the 2-bit counter and the selection circuits is referred to portionsas discussed in connection with FIGS. 36A, 36B and 34. The outputs RCA0and RCA1 of the data transfer control counter 348 and their complements{overscore (RCA0)} and {overscore (RCA1)} may be properly time delayedsignals according to {overscore (CAS)} latency values or the systemclock in order to control a data transfer timing on data lines.

FIG. 46 is a drawing showing a schematic circuit diagram for the readdata transfer clock generator 356 for generating read data transfersignal RDTP0 to RDTP3 which are used in the data output multiplexer.Referring to the drawing, the generator 356 comprises NAND gates 498 fordecoding column address signals RCA0 and RCA1 and their complements{overscore (RCA0)} and {overscore (RCA1)}, delay circuits 500 forreceiving the decoded signals and producing read data transfer signalswith different time delays according to {overscore (CAS)} latencyvalues, and NAND gates 496 for outputting the read data transfer signalsin a read operation and resetting their outputs to low levels in a writeoperation. The outputs of NAND gates 496 become high in response to thesignal φ_(EWDC) being at a high level in a write operation. Each of NANDgates 498 serves as a decoder outputting low in response to two inputsof high levels. Each delay circuit 500 includes a shift register 503having a plurality of data paths and switches 497, 501 and 502respectively connected to the data paths, and serves to provide adifferent time delay via a selected switch according to {overscore(CAS)} latency signals CL3 and CL4. Referring to FIG. 51B, where initialexternal column addresses A₀ and A₁ are respectively at a high level(=1) and a low level (=0), illustration is made on a timing diagram forcolumn address signals RCA0 and RCA1 for controlling data transfer andread data transfer signals RDTP0 to RDTP3. Since the {overscore(CAS)}latency value is 3, switches 502 are turned on.

FIG. 47 shows a schematic circuit diagram of a circuit for generatingthe signal φ_(CL) being used in the data output multiplexer 268.Referring to the drawing, after the activation of {overscore (CAS)}, thehigh-going pulse φ_(C) renders high the output of a flip-flop 504 via adelay circuit 505. On the other hand, if one of {overscore (CAS)}latency signals CL3 and CL4 is high, the output of a NAND gate 506maintains high. Thus, the signal φ_(CL) goes high. Then if φ_(C) goeslow, the signal φ_(CL) will go low after a delay of about one cycle ofφ_(CLK) in case of a high level signal CL3, while the signals φ_(CL)will go low after a delay of about 2 cycles of φ_(CLK) in case of a highlevel signal CL4. However, if CL3 and CL4 are all low, i.e., where{overscore (CAS)} latency is either 1 or 2, φ_(CL) is always low sincethe output of NAND gate 506 is low.

FIG. 49 shows a timing diagram of {overscore (CAS)} interrupt readoperation after activation of {overscore (RAS)}. The operation isperformed at the {overscore (CAS)} latency of 3 and the burst length of4 with system clock of 66 MHZ. At time t₁, a read command is issued withexternal column addresses A₀, A₁, A₂, . . . , A8=1, 0, 0, . . . , 0. Attime t₃, a {overscore (CAS)} interrupt read command is issued withexternal column addresses A₀, A₁, A₂, . . . , A8=0, 1, 0, . . . , 0.Then, at t₃ and t₄, i.e., just before and after the issuance of the{overscore (CAS)} interrupt read command, column address signals RCA0and RCA1 are identical as a low level and a high level. Thus, read-outdata is transferred in series via the same data line pairs DIO₂,{overscore (DIO₂)} at times t₃ and t₄. It may be seen in FIG. 49C thatread-out data was high just before the {overscore (CAS)} interrupt,while read-out data was low immediately after the {overscore (CAS)}interrupt. Then, as shown in the timing diagram of DIO₂ between t₃ andt₅ in FIG. 49C, serial data, i.e., 1,0 is transferred on the data lineDIO₂. Thus, as shown in FIG. 25, if means 276 for isolating betweenserial registers 274 and 278 are not provided therebetween, the serialdata is sequentially latched into the serial registers 274 and 278, andtransferred only in series to the data output buffer via transfer switch280 which is turned on by the read data transfer signals RDTP2. However,since the operation speed of semiconductor circuit varies according toambient conditions such as ambient temperature, it is essentiallynecessary to provide means for preventing serial data contention due tovariations of the operation speed of the transfer switch 280 or dataoutput buffer. The signal φ_(CL) is used as a signal for isolatingbetween serial registers 274 and 278 to prevent such a data contention.It is to be understood that the data contention between two serial datamay be prevented by the high level pulse φ_(CL) indicating as P in FIG.49C.

FIG. 48 shows a schematic circuit diagram of the write data transfergenerator write data transfer signals WDTP0 to WDTP3 for use in the datainput demultiplexer 314. The generator 358 comprises NAND gates fordecoding column address signals RCA0 and RCA1 and their complements{overscore (RCA0)} and {overscore (RCA1)}, a synchronization circuit 510for synchronizing the decoding signals from the NAND gates with thesystem clock φ_(CLK) and producing synchronized write data transfersignals, and NAND gates 512 for gating the synchronized write datatransfer signals. A line 514 stays at a low level to reset all of thegates 512 during a read operation, a {overscore (CAS)} interrupt or adata input/output masking operations thereby causing the signals WDTP10to WDTP3 to go low. Reference numeral 516 represents a delay circuit. Asshown in FIG. 33, by a high level address signal RCA0 and a low leveladdress signal RCA1, a high level pulse signal WDTP1 is generated andnext sequential address signals RCA0 and RCA1, which are respectively alow level and a high level, generates a high level pulse signal WDTP2.

6. Data Line Precharge Circuit

Data line precharge circuit is a circuit for generating control signalsto precharge I/O lines, PIO lines and DIO lines. According to thepresent invention, data transfer and precharging between lines on datapaths are sequentially performed in turn. To perform such a prechargeoperation, column address signal CA1 produced from external columnaddress A₁ is utilized.

FIG. 50 shows a schematic circuit diagram of a circuit for generatingcontrol signals to precharge I/O lines and PIO lines. RA11 and CA9 arebank selection signals as discussed above, and I/O lines and PIO linesare initialized to precharge states. Thus, PIOPR1 and IOPR1 and theircomplements {overscore (PIOPR1)} and {overscore (IOPR1)} are at highlevels. After activation of {overscore (CAS)}, once φ_(CP) goes from alow level to a high level (φ_(YEi) maintains a high level), NAND gates518 are then enabled. If CAI is at a low level ({overscore (CAI)} at ahigh level), precharge signals PIOPR1 and IOPR1 maintain high levelswhile {overscore (PIOPR1)} and {overscore (PIOPR1)} go to low levels.Thus, in FIG. 24, if BLS is high, I/O line pairs I/O₂, {overscore(I/O₂)} and I/O₃, {overscore (I/O₃)} are continuously precharged.However, I/O₀, {overscore (I/O₃)} and I/O₂, {overscore (I/O₂)} ceaseprecharging to be ready for data transfer. PIO line pairs PIO₂,{overscore (PIO₂)} and PIO₃, {overscore (PIO₃)}, as shown in FIG. 28,are also precharged in the same manner. Then, if CAI goes to a highlevel, lines I/O₀, {overscore (I/O₀)}, I/O₁, {overscore (I/O₁)}, PIO₀,{overscore (PIO₀)}, PIO₁ and {overscore (PIO₁)} are converselyprecharged. On the other hand, a short low level pulse φ_(CP) generatedafter activation of {overscore (CAS)} in a {overscore (CAS)} interruptoperation renders all of precharge signals PIOPR1, {overscore (PIOPR1)}and {overscore (IOPR1)} to become high level pulses. Thus, prior toreceipt of column addresses upon {overscore (CAS)}interrupt, all of I/Oline pairs and PIO line pairs are precharged. By such a {overscore(CAS)} precharge, internal operations may be performed at a high speedwith no wait. Reference numeral 520 represents a delay circuit.

FIG. 51 shows a schematic circuit diagram of a circuit for generatingcontrol signals to precharge DIO lines. In the same manner as discussedabove, once φ_(CP) goes to a low level, DIO line precharge signal DIOPR1and its complement {overscore (DIOPR1)} go high, and signal WCA1 and itscomplement {overscore (WCA1)} go low, thereby precharging all of DIOlines. That is, this is in case of a {overscore (CAS)} interruptoperation. If φ_(CP) goes to a high level and CA1 is at a low level({overscore (CA1)} is at a high level), signals DIOPR1 and WCA1respectively maintain the high level and the low level while {overscore(DIOPR1)} and {overscore (WCA1)} respectively go to a low level and ahigh level. Thus, during a read or a write operation, precharge circuits263 c and 263 d of FIG. 25 maintains on states while the circuits 263 aand 263 b thereof are turned off. Then, line pairs DIO₂, {overscore(DIO₂)} and DIO₃, {overscore (DIO₃)} keep precharging while DIO₀,{overscore (DIO₀)} and DIO₁, {overscore (DIO₁)} are ready for datatransfer. In case of the write operation, transistors 318 c and 318 d ofFIG. 27 maintain on states and transistors 318 a and 318 b thereof areturned off, thereby causing buffers 324 c and 324 d to keep off statesand buffers 324 a and 324 b to transfer data depending on data statesstored in latches 320. Then if CA1 goes to a high level, operationscontrary to above mentioned ones are performed.

FIG. 52 is a schematic circuit diagram of a circuit for generating bankselection signals for use in the PIO driver 330 shown in FIG. 28. Once awrite command is issued, φ_(WR) and φ_(CP) then go to high levels. Atthis time, when RA11 or CA9 is at a low level, DTCP1 is latched to ahigh level and thereby the first bank is selected. Where prechargecommand is issued to the first bank, φ_(YE1) goes to a low level andthereby the first bank selection signal DTCP1 then goes to a low level.On the other hand, where a write command is issued to the second bankduring the write operation for the first bank, a flip-flop 522′ islatched to a low level and thereby a second bank selection signal DTCP2then goes to a high level. Each of DTCP1 and DTCP2 is connected to PIOdriver 330 associated with corresponding bank. Referring to FIG. 28,when bank selection signal DTCPi and block information signals BLS areall at high levels, switches 332 are enabled, thereby allowing data oncorresponding DIO lines to be transferred.

7. Data Output Buffer Control Circuit

Data output buffer control circuit is a circuit for controlling dataoutputs from the data output buffer 284 shown in FIG. 26. It is requiredthat the data output buffer outputs data at eery predetermined risingedges of the system clock CLK in a read operation. Since the synchronousDRAM must output data information only within a given time period set bythe {overscore (CAS)} latency and the burst length, it is to bepreferred that data output therefrom is precluded outside the given timeperiod in order to as well increase the performance of the chip asprevent power consumption. Also, since one cycle time of the systemclock of a predetermined frequency (33 MHZ in this embodiment) or lessis long, it is meaningless to output data in synchronism with the systemclock CLK.

FIG. 53 is a schematic circuit diagram of a control circuit forgenerating a control signals to inhibit data output of the data outputbuffer 284. NAND gate 524 outputs a low level in a write operation. Aclock signal φ_(CF) stays a high level for one clock cycle of φ_(CLK)going to the high level at the first rising edge of φ_(CLK) afteractivation of {overscore (CAS)}. Likewise, φ_(WRCP) stays a high levelfor one clock cycle of φ_(CLK) after the activation of {overscore (WE)}.Where {overscore (CAS)} and {overscore (WE)} are all activated, the NANDgate 524 generates the low level, thereby allowing a signals φ_(TRST) togo low. Also, when data output masking is requested by the externalsignal DQM, the DQM buffer 342 shown in FIG. 31 generates the low levelclock signal φ_(DQMF) as shown in FIG. 32. Thus, the NAND gate 526generates a high level pulse. This results in generating a row levelpulse φ_(TRST). Likewise, the signal φ_(TRST) also becomes low with thesignals COSDQ being at a high level after the delay depending on{overscore (CAS)} latency j following the completion of the burstlength. Thus, the output of the data output buffer 284 shown in FIG. 26becomes a high impedance in response to the low level signal φ_(TRST).Consequently, the data output buffer 284 inhibits data output at therising edge of next system clock CLK after the issuance of the dataoutput masking signal DQM. Also, upon the completion of the burst dataoutput, the output of the buffer 284 becomes the high impedance.

Where external system clock of 33 MHZ or less is used, a control signalφ_(YEP) may be coupled to the {overscore (CAS)} latency signal CL1 so asto output data irrespective of the internal system clock φ_(CLK). Sincethe {overscore (CAS)} latency signal CL1 keeps a high level at such asystem clock, the signal φ_(YEP) is at a high level. Thus, in the dataoutput buffer 284 of FIG. 26, transfer switches 286 and 286′ are alwaysturned on and thereby not under the control of the system clock φ_(CLK).However, when system clock of a frequency above 33 MHZ is used, thesignal CL1 is at a low level and the signal φ_(YEP) is also at a lowlevel. Thus, the transfer switches 286 and 286′ are turned on and offunder the control of the system clock φ_(CLK).

Operation

Explanation will be now made on operation and using way of the presentsynchronous DRAM.

Referring to FIG. 41, illustration is made on a timing chart showing aread operation at the burst length of 4 and the {overscore (CAS)}latency of 3, using an external system clock of 100 MHZ . At time t₁,activation command is issued. External addresses input along with theactivation of {overscore (RAS)}. Then {overscore (RAS)} buffer 56produces the signal φ_(RP) and then generates the bank selection{overscore (RAS)} signal φ_(RCi) defining one of the first and secondbanks 12 and 14 with the external address A₁₁. The row master clockgenerator 62 of FIG. 19 generates the row master clock φ_(Ri) in receiptof the signal φ_(RCi) The row address buffer 60 responds the row masterclock φ_(Ri) to generate row address signals which are fed to the rowdecoder 18 of selected bank. In response to the row address signals, therow decoder 18 generates a block information signal BLS representativeof a selected sub-array in each of the first to the fourth memory cellarrays and a signal selecting a word line in the selected sub-array.Sensing operation, which drives word lines selected by the word lineselection signals and then develops data on corresponding bit lines, isperformed by conventional techniques. After the completion of {overscore(RAS)} chain, the row control clock generator 64 generates the signalφ_(RCDi) guaranteeing the {overscore (RAS)}−{overscore (CAS)} delay timet_(RCD). At time t₂, read command is issued and column addresses areinputted to the column address buffer 344. In response to the {overscore(CAS)} signal being at the low level at the time t₂, the buffer 344generates pulse signals tics φ_(C), φ_(CA), φ_(CP) and BITSET. Thesignal φ_(CAR) for controlling circuits associated with column addresssignal generation is generated from the column address reset signalgenerator 354 in response to the pulse signal φ_(C) and the signalφ_(YECi) which is generated from the column enable clock generator 66 inresponse to φ_(RCDi). The column address buffer 344 outputs columnaddress signals CA0 to CA9 in response to the pulse signal φ_(CA) fromthe {overscore (CAS)} buffer and the signal φ_(CAR). Thus, since thecolumn address signals generated from the column address buffer 344responsive to the column address enable/disable signal φ_(CAR), which isgenerated by the φ_(RCDi) signal representative of the completion of{overscore (CAS)} chain, and the φ_(C) signal representative of theactivation of {overscore (CAS)}, the time duration from the activationof {overscore (CAS)} (time t₂) until the output of the column addresssignals becomes considerably short. After the transition of the φ_(CAR)signal to the high level, the burst length counter 350 carries outcounting operation of the system clock φ_(CLK) to detect the burstlength. In response to count signals CNT0 and CNT1 from the burst lengthcounter 350, the burst length detector 352 generates the burst endsignal COSI and the COSR signal representative of the burst length afterthe activation of {overscore (CAS)}. The detector 352 also producesCOSDQ signal delayed by given clock cycles depending on a preset{overscore (CAS)} latency value from the signal COSR to control the dataoutput buffer 284 so as to provide data for the time period of dataoutput which is defined by the burst length. Thus, since the {overscore(CAS)} latency equals 3, the signal COSDQ is a signal delayed byapproximately two cycles of φ_(CLK) from the signal COSR. Thus, theCOSDQ signal is at the low level for the period of time defined by the{overscore (CAS)} latency and the burst length (the time durationbetween t₃ and t₆).

The column address counter 346 loads column address signals from thecolumn address buffer 344 in response to the pulse signal BITSET fromthe {overscore (CAS)} buffer and the column address enable signalφ_(CARC), and then generates column address signals PCA0 to PCA8 insequence, counting the clock CNTCLK9 according to the burst length andthe address mode. The column address buffer 344 generates sequentialcolumn address signals CA0 to CA8 composed of initial column addressesand the column address signals PCA0 to PCA8.

FIG. 41 shows the timing chart at a binary address mode ((φ_(INTEL)=0)where initial external column address A₀ is high and the remainingexternal column addresses A₁ to A₈ are all low. Since the burst lengthwas set to 4, only the burst length signal SZ₄ stays at a high level.Thus, only the lower two stages ST1 and ST2 of the first counter portionconstituting the column address counter 346 of FIG. 35 executes thebinary counting operation. Since the counting operation is performed at100 MHZ, the clock CNTCLK9 is identical to the system clock φ_(CLK).Thus, the outputs RCA0 and RCA1 of the data transfer control counter 348are identical to the outputs PCA0 and PCA1 of the column address counter346. The outputs RCA0 and RCA1 of the counter 348 are fed to the readdata transfer clock generator 356, thereby generating read data transferpulses RDTP0 to RDTP3 therefrom.

On the other hand, column address signals CA0 to CA8 from the columnaddress buffer 344 are fed to the column decoder 24, and the columnpredecoder 436 of FIG. 39A produces partly overlapped predecode signalsDCA{overscore (1)} {overscore (2)} and DCA1{overscore (2)} with thesuccessive column address signals CA1 and CA2. The main column decoder444 of FIG. 40 receives the predecode signals to generate columnselection signals CSL0 and CSL1. Since the column selection signal CSL0allows data developed on bit line pairs to be transferred to the firstI/O line pairs I/O₀, {overscore (I/O₀)} and I/O₁, {overscore (I/O₁)},data on the first I/O line pairs, which is produced by the first pulse532 of the column selection signal CSL0, inputs to the I/O senseamplifier via corresponding I/O line selection circuit and correspondingfirst PIO line pairs. In response to the activating signal 535 as shownin FIG. 41C, the I/O sense amplifier amplifies data on the first PIOline pairs to output to corresponding first data line pairs DIO₀,{overscore (DIO₀)} and DIO₁, {overscore (DIO₁)}. At this time, since theDIO line precharge signal DIOPR1 is at a high level, the second dataline pairs DIO₂, {overscore (DIO₂)} and DIO₃, {overscore (DIO₃)} are inprecharging states. Data transferred via the first data line pairs isstored into the register 278 in the data output multiplexer 268 of FIG.25. Data transferred via the data line pair DIO₁, {overscore (DIO₁)} ofthe first data line pairs is selected by the pulse RDTP1 and theninputted to the data output buffer via the common data line pair CDL,{overscore (CDL)}, the data output latch 282 and the data output linepair DO, {overscore (DO)}. In the same manner as discussed above,parallel data on the second I/O line pairs I/O₂, {overscore (I/O₂)} andI/O1 ₃, {overscore (I/O₃)}, which is generated by the pulse 533 ofcolumn selection signal CSL1, is then inputted in series to the dataoutput buffer. Last data on the I/O line pair I/O₀, {overscore (I/O₀)}of the first I/O line pairs, which is generated by the second pulse 534of the column selection signal CSL0, is then inputted to the data outputbuffer. If read-out is 1,0,1,0, the data output buffer is enabled by thehigh level pulse φ_(TRST), and its output DOUT is like the illustrationof FIG. 41C. Thus, when the signal φ_(TRST) is low the data outputbuffer 284 becomes a high impedance and thereby prevents unnecessaryoperation thereof. It can be seen that the first data is generated atthe rising edge of the third clock of the system clock CLK after theactivation of {overscore (CAS)}, and continuous 4-bit data is outputtedin synchronism with the system clock CLK.

FIG. 33 is the timing chart showing a write operation at the {overscore(CAS)} latency of 2 and the burst length of 4, using a system clock of66 MHZ. The timing of FIG. 33 is also of the case where externaladdresses A₀ and A₁ to A₈ are respectively applied with a high level andlow levels in the same manner as above-mentioned read operation, and theinput data DIN to the data input buffer is a serial data of 1,0,1,0. The{overscore (RAS)} chain operation is performed as previously discussed,and the burst length signal COSR is generated by the burst end signalCOSI. Sequential column address signals RCA0 and RCA1 for generatingwrite data transfer pulses WDTP0 to WDTP3 are produced by column addresssignals CA0 and CA1. Write command is issued at time t₂, and writecontrol signals φ_(WR) and φ_(EWDC) are produced from the {overscore(WE)} buffer 340 by the low level signal {overscore (WE)}. In responseto the signals RCA0 and RCA1, the write data transfer clock generator358 generates write data transfer pulses WDTP0 to WDTP3 for converting aserial data to a parallel data. The input data DIN inputting via thedata input buffer 312 is outputted on the input line DI as the serialdata synchronized with φ_(CLK) as shown in FIG. 33. The data inputdemultiplexer 314 produces the parallel data on the data lines{overscore (DIO₁)}, DIO₂, {overscore (DIO₃)} and DIO₀ under the controlof control signals WCA1 and {overscore (WCA1)} and the write datatransfer pulses WDTP0 to WDTP3, having the timing as shown in FIG. 33.The parallel data is fed to corresponding I/O bus via the PIO linedriver 330 under the control of control signals IOPR1 and {overscore(IOPR1)}, and then written into corresponding memory cells via bit linesselected by the column selection signals.

FIG. 49 is the timing chart showing the {overscore (CAS)} interrupt readoperation at the {overscore (CAS)} latency of 3 and the burst length of4, using a system clock of 66 MHZ . At the read command of time t₁,external addresses A₀ and A₁ to A₈ are respectively applied with a highlevel and low levels, and at the {overscore (CAS)} interrupt readcommand of time t₃, external addresses A₁ and A₀ and A₂ to A₈ arerespectively applied with a high level and low levels. This {overscore(CAS)} interrupt read operation is identical to the previously discussedread operation, excepting that the last 2-bit data of the data, whichmust be read out by the read command issued at time t₁, can never beread out by the {overscore (CAS)} interrupt command issued at time t₃.Referring to FIG. 49, explanation will be made in brief. The activationcommand, i.e., the {overscore (RAS)} activation command is issued at twocycles of CLK before time t₁. Then since operation of {overscore (RAS)}chain with row addresses is identical to that as previously discussed,explanation of this operation will be omitted. The read command isissued at time t₁, and the column predecode signal DCA{overscore (1)}{overscore (2)} a from the column predecoder (shown in FIG. 39A) thenbecomes high with CA1 and CA2 being at low levels. Then, the columnselection signal CSL0 includes the high level pulse 600, as shown inFIG. 49B, with CA2 to CA8 being always at low levels. After thetransition of CA1 from the low level to the high level, the columnpredecode signal DCA1{overscore (2)} becomes high, overlapping one endportion of the signal DCA{overscore (1)} {overscore (2)}, and therebythe column selection signal CSL1 has the high level pulse 601. Once the{overscore (CAS)} interrupt read command is issued at time t₃, the{overscore (CAS)} buffer 338 then generates the signal BITSET of pulse602. The burst length counter 350 is then reset by the pulse 602 andre-starts a binary counting operation with the system clock φ_(CLK).After counting the burst length of 4, the counter 350 generates theburst end signal COSI of pulse 603. Then, the burst length detector 352produces the low level signal COSR indicating of a burst length from thefirst read command with the pulse φ_(C) and the signal COSR, and thenoutputs the signal COSDQ indicating of a data read-out time period withthe signal COSR and the {overscore (CAS)} latency signal. Thus, it canbe seen that a total 6-bit data may be read out. The column addressbuffer 344 shown in FIG. 34 latches external column addresses inputtedupon {overscore (CAS)} interrupt (at time t₃) by the high level pulseφ_(CA) from the {overscore (CAS)} buffer 338, and produces successivefour column address signals with the help of the column address counter346. Thus, column address signal CA1, which is latched by the externalhigh level address A₁ inputted at time t₃, maintains high for about twoclock cycles after the transition of φ_(CA) to the low level since theleast significant column address signal CA0 stays at the low level.Then, since CA2 to CAS are all low at this time, the column selectionsignal CSL1 becomes the high level pulse 604. After the transition ofCA1 to the low level, CA1 and its complement {overscore (CA1)}respectively stay low and high for about two clock cycles. However, thelow-going signal φ_(CAR) causes CA1 and {overscore (CA1)} to go low.This results in allowing the column selection signal CSL0 to become thehigh level pulse 605. On the other hand, with column addresses A₀ and A₁being respectively high and low at t₁, and with column addresses A₀ andA₁, being respectively low and high at t₃, read data transfer pulsesRDTP0 to RDTP3 are generated as shown in FIG. 49b.

Data on bit line pairs is transferred to first I/O line pairs by thepulse 600 of CSL0, and then transferred to first data pairs DIO₀,{overscore (DIO₀)} and DIO₁, {overscore (DIO₁)} via first PIO linepairs. FIG. 49C shows where a high level data and a low level data arerespectively transferred in parallel on DIO₀ line and DIO₁ line. Thisparallel data is stored into latches 278 a and 278 b in the data outputmultiplexer 268 of FIG. 25, and the pulse 606 of RDTP1 then causes thestored data of the latch 278 b associated with the line DIO₁ to outputtherefrom. Consequently, the data output buffer outputs the low leveldata RD1. Parallel data selected by the pulse 601 of CSL1 is transferredto second data line pairs DIO₂, {overscore (DIO₂)} and DIO₃, {overscore(DIO₃)} via second I/O line pairs and second PIO line pairs. It can beseen that data on DIO₂ and DIO₃ is respectively high and low. The pulse607 of RDTP2 selects data stored into the latch 278 cand the data outputbuffer then outputs the high level data RD2. Likewise, parallel dataselected by the pulse 604 of CSL1 is transferred to data lines DIO₂ andDIO₃. The drawing of FIG. 49C shows that a low level data and a highlevel data are transferred on data lines DIO₂ and DIO₃, respectively.The transfer switch 276 of FIG. 25 becomes an off state with the highlevel pulse P of φ_(CL). However, after the data, which was stored intothe latch 278 c via the line DIO₂ in the previous operation, has beentransferred toward the data output buffer by the pulse 607 of RDTP2, thepulse P goes low. Then, the switch 276 becomes on. Thus, data on thedata lines DIO₂ and DIO₃ is respectively stored into latches 278 c and278 d. Data stored into the latch 278 c is then outputted by the pulse607 of RDTP2 and thereby the data output buffer 284 outputs the lowlevel data RD3. Data stored into the latch 278 d is then outputted bythe pulse 608 of RDTP3, thereby resulting in outputting the high leveldata RD4 from the data output buffer 284. Likewise, data selected by thepulse 605 of CSL0 is transferred to first data line pairs. It can beseen in the drawing that a low level data and a high level data arerespectively transferred in parallel on data lines DIO₀ and DIO₁. In thesame manner as discussed above, this parallel data is selected insequence by the pulses 609 and 610 shows in FIG. 49B, and the dataoutput buffer 284 then outputs the low level data RD5 and the high leveldata RD6 in sequence. The data output buffer 284 then becomes a highimpedance with the high level signal COSDQ.

FIG. 54 is a timing chart showing various operations at the {overscore(CAS)} latency of 2 and the burst length of 4, using only one selectedbank. Commands are given as follows: activation command at t₁, readcommand with external column addresses CA0 at t₂, {overscore (CAS)}interrupt read command with external column addresses CB0 at t₃,{overscore (CAS)} interrupt write command with external column addressesCCO at t₇, {overscore (CAS)} interrupt write command with externalcolumn addresses CD0 at t₁₀, precharge command at t₁₂ and datainput/output masking command at t₆, t₉, t₁₂ and t₁₃. Data QA0 and QA1respectively output at t₃ and t₄ due to the read command issued at t₂,and data QB0 and QB1 successively output at t₅ and t₆ due to the readcommand issued at t₃. At t₇, data output is inhibited and stays in ahigh impedance state due to the data output masking command issued att₆. At t₈ and t₉, write data DC0 and DC1 respectively input due to thewrite command at t₇. The data input masking command at t₉, write dataDC0 and DC1 respectively input due to the write command at t₇. The datainput masking command at t₉ interrupts receipt of write data at timet₁₀. Likewise, at t₁₁ and t₁₂, write data DD0 and DD1 are respectivelyinputted due to the write command at t₁₀. The data input masking commandissued at t₁₂ and t₁₄ after the precharge command at t₁₂.

FIG. 55 is a timing chart showing various operations at the {overscore(CAS)} latency of 2 and the burst length of 4 with one selected bank.Read, write and data input/output masking operations are the same asthose of FIG. 54. After issuance of freeze command at t₁, generation ofa pulse of internal system clock φ_(CLK) corresponding to the pulse 536of the system clock CLK is inhibited. Thus, the output of data at t₃ isfrozen so as to output the same data as the output of data at t₂.Likewise, the internal system clock, in which the generation ofcorresponding pulse is precluded, causes operation of the column addresscounter to be frozen, thereby inhibiting writing of data at t₅.

FIG. 56 is a timing diagram showing a read operation at the {overscore(CAS)} latency of 2 and the burst length of 4 with two banks. Withactivation command of the first bank at t₁, and with read command at t₂,successive data QA0 to QS3 outputs from time t₃. With activation commandof the second bank at t₃, and with read command at t₄, successive dataQB0 to QB3 also outputs from time t₅. At time t₆, simultaneous prechargecommand is issued at t₆.

FIG. 57 is a timing diagram showing an interleave read operation withthe {overscore (CAS)} latency of 2 and the burst length of 4. Activationcommand for the first bank is issued at time t₁, and that for the secondbank is then issued at time t₂. Thus, data QA0 to QA3 is read out fromthe first bank from time t₃. At the same time, activation command forthe second bank is issued at t₃. At time t₄, read command is issued forthe second bank selected with the high level column address A₉. Then,after output of successive 4-bit data QA0 to QA3, read-out data QB0 andQB1 outputs from the second bank with no gap. At time t₅, read commandis issued for the first bank with the low level column address A₉,thereby successively outputting read-out data QC0 and QC1 from the firstbank. Read command is then issued for the second bank at time t₆,thereby outputting read-out data QD0 and QD1. Precharge command is thenissued for the first bank at time t₇. Read command is them issued forthe second bank at time t₈, thereby outputting read-out data QE0 to QE3.Precharge command is issued for the second bank with external addressesA₁₀ and A₁₁ at time A₉.

Explanation has been made on various operation modes with a single datainput/output pad in connection with FIGS. 54 to 57. However, it shouldbe noted that the present embodiment has eight data input/output padsand various applications are also possible.

Other Embodiments

As discussed hereinabove, the present synchronous DRAM has been modifiedwith pulse {overscore (RAS)}. However, the synchronous DRAM of thepresent invention may be embodied with the level {overscore (RAS)}.Various operation commands for the level {overscore (RAS)} have beenalready explained. In order for the present synchronous DRAM to operatewith the level {overscore (RAS)}, some circuits need modifications, butothers may be used with no modification.

FIG. 58 is a drawing showing a schematic circuit diagram for a{overscore (RAS)} buffer using the level {overscore (RAS)}. Referring tothe drawing, an input buffer 70 and a synchronization circuit 108 whichconstitute the level {overscore (RAS)} buffer 538 are the same inconstructions and operations as the {overscore (RAS)} buffer 56 for thepulse {overscore (RAS)} showing in FIG. 9. The output of thesynchronization circuit 108 is connected in common with a first{overscore (RAS)} signal generator 540 for the first bank and with asecond {overscore (RAS)} signal generator 542 for the second bank via. alatch 550. The first {overscore (RAS)} signal generator 540 comprises aflip-flop 545 for storing a first bank {overscore (RAS)} signal inresponse to a bank selection signal {overscore (SRA11)} produced by anaddress A₁₁. The flip-flop 545 is a NAND type flip-flop comprised ofNAND gates 544 and 546. One input terminal of the flip-flop 545 isconnected to the output of a NOR gate 548, and the other input terminalof the flip-flop 545 receives a {overscore (RAS)} signal from thesynchronization circuit 108. The NOR gate 548 receives the bankselection signal {overscore (SRA11)} on its first input terminal and asignal on its second input terminal which is staying at a high levelduring a refresh, a mode set or a test operation. The construction ofthe second {overscore (RAS)} signal generator is the same as that of thefirst {overscore (RAS)} signals generator. Thus, upon the activation of{overscore (RAS)}, if the external address A₁₁ is low, i.e., {overscore(RAS)} signal φ_(RC1) is then latched to a high level. At this time,since the NOR gate 548′ of the second {overscore (RAS)} signal generator542 outputs high, the flip-flop 545′ maintains the previous state. Thatis, if upon the activation of {overscore (RAS)} in the previousoperation, A₁₁ was high, i.e., SRA11 was high, the second bank{overscore (RAS)} signal φ_(RC2) keeps high. On the other hand, if{overscore (RAS)} goes from a low level to a high level, the latch 550latches a high level at the rising edge of the next system clockφ_(CLK). Thus, NAND gates 546 and 546′ each receives a low level, andthereby the signals φRC1 and φ_(RC2) becomes low. That is, both banks goto precharge states. In addition, since O_(RFH) is low during a refresh,and O_(WCBR) is low during a mode set operation, the signals φ_(RC1) andφ_(RC2) are all high in such operations. Signals φ_(RL1) and φ_(RL2) arefaster signals than the signals φ_(RC1) and φ_(RC2).

FIG. 59 is a drawing showing address buffers for generating specialaddresses SRA10 and SRA11. These address buffers is independent buffersseparated from the row and column address buffers. The address buffer552 for producing SRA10 in response to an address A₁₀ is used in thepulse {overscore (RAS)}, but not in the level {overscore (RAS)}. Theaddress buffer 552 has the same construction as previously mentionedbuffers each comprised of the input buffer 70 and the synchronizationcircuit 108. The address buffer 554 for producing SRA11 in response toan address A₁₁ comprises a transfer switch 556 which is turned on inresponse to signals φ_(RC1) and φ_(RC2) produced in case of level{overscore (RAS)}. The transfer switch 556 is turned off by activationof either the first or the second bank and also serves to prevent fromchanging a logic level of the signal SRA11 with the system clock φ_(CLK)after activation of one of both banks. In case that the address buffer554 is used for the pulse {overscore (RAS)}, it may be modified so thatthe output of the latch 558 becomes SRA11.

FIG. 60 is a schematic circuit diagram of a level {overscore (RAS)}control circuit for generating a mode set control signal O_(WCBR) and arefresh clock O_(RFH) in case of the level {overscore (RAS)}. In themode set control signal generator 200 of FIG. 14 used in the pulse{overscore (RAS)}, the transfer switches are gated by the signal φ_(RP).However, in case of the level {overscore (RAS)}, the transfer switchesare gated by a signal being produced by the signals φ_(RL1) and φ_(RL2)in place of the signals φ_(RP). This is to generate the signals O_(WCBR)and O_(RFH) with faster signals φ_(RL1) and φ_(RL2) than φ_(RC1) andφ_(RC2). Its operation is the same as that explained in connection withFIG. 14.

FIG. 61 is a drawing showing an operation timing charge of thesynchronous DRAM using the level {overscore (RAS)}. The operation timingchart as shown in this drawing has relationship with that using thepulse {overscore (RAS)} as shown in FIG. 54. In the drawing of FIG. 61,a precharge command is issued at time t₁. Remaining operations are thesame as those of the pulse {overscore (RAS)}.

As explained hereinabove, the system design and using ways of thepresent synchronous DRAM have been explained in detail. Althoughembodiments of the present invention have been explained in connectionwith a synchronous DRAM, it would be obvious to those skilled in the artthat the present invention may also be applied to other semiconductormemories.

What is claimed is:
 1. A multi-bank dynamic random access memory device,comprising: a plurality of memory banks that are operable in either oneof an active mode and a precharge mode at any one time; and a rowaddress strobe buffer that generates first and second row address strobeclocks in response to a row address strobe signal and an internal clockthat is synchronized to an external clock, said row address strobebuffer comprising a control circuit that is responsive to a first rowaddress signal, and sets the first and second row address strobe clocksat respective inactive levels that enable at least first and secondmemory banks in said plurality of memory banks to enter their respectiveprecharge modes during overlapping time intervals.
 2. The memory deviceof claim 1, further comprising a write enable buffer; and wherein thefirst and second row address strobe clocks are set at their respectiveinactive levels in-sync with a leading or trailing edge of a controlsignal generated by said write enable buffer.
 3. The memory device ofclaim 2, wherein the leading or trailing edge of the control signalgenerated by said write enable buffer occurs in-sync with the externalclock.
 4. The memory device of claim 2, wherein the leading or trailingedge of the control signal generated by said write enable buffer occursin-sync with the external clock when a write enable signal and the rowaddress strobe signal are active and a column address strobe signal isinactive upon occurrence of a leading edge of the external clock.
 5. Thememory device of claim 1, wherein said row address strobe buffer isresponsive to a second row address signal; and wherein a complement ofthe second row address signal constitutes a bank selection signal.
 6. Amulti-bank dynamic random access memory device, comprising: a pluralityof memory banks operable in either one of an active cycle and aprecharge cycle at any one time; input means for receiving an externalprecharge command that commences the precharge cycle; means for latchinga precharge logic level and synchronizing the precharge logic level toone of a rising edge or a falling edge of an internal clock synchronizedto an external clock, in response to the received external prechargecommand and an activation of an address signal for all bank precharge,and at the same time, precharging all of the memory banks by the latchedprecharge logic level; a synchronizing circuit that in response to anexternal row address strobe signal and an internal clock, generates arow address strobe clock synchronized to the internal clock; and amultifunction control circuit that controls output of a first rowaddress strobe clock and a second row address strobe clock, whichactivate and deactivate the first and second memory banks, in responseto an external address, an external write control signal and theexternal row address strobe signal.
 7. The memory as claimed in claim 6,wherein each clock output of the multifunction control circuit iscoupled to a respective latch.
 8. The memory as claimed in claim 7,wherein the multifunction control circuit disables the first and secondrow address strobe clocks in response to an automatic precharge signal.9. The memory as claimed in claim 8, further comprising pull-downtransistors for pulling down a level of the first and second row addressstrobe clocks in response to the automatic precharge signal.
 10. Anintegrated circuit memory device, comprising: first and second memorybanks that can be disposed in respective active and precharge modes; anda row address strobe buffer that generates first and second row addressstrobe clocks, said row address strobe buffer comprising a controlcircuit that, in response to an address signal and a row address strobesignal, sets the first and second row address strobe clocks atrespective inactive levels that enable said first and second memorybanks to enter their respective precharge modes during overlapping timeintervals.
 11. The memory device of claim 10, wherein said row addressstrobe buffer further comprises: an input buffer that receives the rowaddress strobe signal; and a synchronization circuit that iselectrically coupled to an output of said input buffer and generates arow address strobe pulse that is in-sync with an internal clock.
 12. Thememory device of claim 11, wherein said control circuit is responsive tothe row address strobe pulse.
 13. The memory device of claim 12, whereinsaid row address strobe buffer switches at least the first row addressstrobe clock from an active level to the inactive level in-sync with aleading or trailing edge of the row address strobe pulse, in response toan active row address strobe signal.
 14. The memory device of claim 11,wherein said row address strobe buffer comprises a gate circuit that isresponsive to at least one of a self-refresh signal and a clock maskingsignal.
 15. The memory device of claim 10, wherein said row addressstrobe buffer comprises a synchronization circuit that generates a rowaddress strobe pulse that is in-sync with an internal clock; and whereinupon receipt of an active row address strobe signal, said row addressstrobe buffer switches at least the first row address strobe clock froman active level to the inactive level in-sync with a leading or trailingedge of the row address strobe pulse.